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Structure and Method to Form Asymmetric Spacer Device Structure

IP.com Disclosure Number: IPCOM000243985D
Publication Date: 2015-Nov-03
Document File: 5 page(s) / 230K

Publishing Venue

The IP.com Prior Art Database

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Page 01 of 5

Title

Structure and Method to Form Asymmetric Spacer Device Structure

Abstract

Disclosed is a structure and method for forming a device structure with an asymmetric spacer.

Problem

Introducing an offset spacer on the drain side (asymmetric drain spacer structure) is useful technique for device performance improvement.

Solution/Novel Contribution

The novel contribution is a structure and method for forming a device structure with an asymmetric spacer.

The method uses an asymmetric spacer on pull down Static Random Access Memory (SRAM) transistors, but not on pass transistors. This is because, for pull downs, Source and Drains are fixed; while for pass, Drain and Source are switching.

Method/Process

The steps for implementing the method follow:

1. Gate pattering on Fin Field Effect Transistor (FinFET) structure

2. Tilted implantation (e.g., Germanium (Ge)) for doping only one side of the dummy gate poly

3. Silicon Nitride (SiN) spacer deposition and doped Source/Drain (S/D) epitaxial growth

4. SiN (CA stopper) and Silicon Dioxide (SiO2) deposition

5. Chemical Mechanical Planarization (CMP) for dummy poly removal

6. Removal of "Ge doped dummy poly region"

7. Deposit another Atomic Layer Deposition (ALD) spacer material to form "Inner Spacer"


8. CMP top of the spacer material

9. Removal of dummy poly gate

10. Perform processes for gate stuck formation


Page 02 of 5

Figure 1: Gate pattering on FinFET structure

Figure 2: Tilted implantation (for ex: Ge) for doping only...