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System Level Link Width Adjustment to Avoid Instantaneous Glitches of Higher Utilization Disclosure Number: IPCOM000243997D
Publication Date: 2015-Nov-04
Document File: 4 page(s) / 62K

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The Prior Art Database


Described is system level link width adjustment to avoid instantaneous glitches of higher utilization.

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System Level Link Width Adjustment to Avoid Instantaneous Glitches of Higher Utilization

In multi-core processors, involving scaling of processor host bus across multiple physical chips using internal bus to maintain coherency leads to a lot of performance advantages. The physical link that extends between two chips in a same planar or to a different planar allows the processor protocol to scale out and interchange information and operate at a system level without having to undergo protocol changes. This feature allowed the processor to scale over different nodes, with the different CPU physically located at various nodes can still access memory on multiple nodes. In other words, threads from various CPU can bound to an application which can still work to give the desired output.

    Normally in a server system containing multiple physical processors in a node and across the node, a need for data request is first floated internal to the chip, then to a group of chips, and then onto a whole system. In this example, any request within a group is assumed to be over the X bus and any request at a system level is assumed to be on A bus, that connects different groups. Power Bus protocol (Host bus) defines the scope of these transactions on various conditions and situations, but the main data movement has to happen through the links in order to acknowledge the requests. This invention is related to the changing of bus width on all the available interfaces, to facilitate power and performance optimization can be achieved by:

· Protocol supported data/command movement routing based on utilization at reduced bandwidth under scenarios of lower utilization.

· Policy initiation by running the system in half-width mode and then moving to full-width mode based on link utilization
o Two options

         § one link only or
§ all the links of the entire system
o Based on actual data seen in that kind/build of the system, · Observe usage patterns across the system to move back and forth between full and half bandwidth mode.

· Historically analyze the traffic study during various parts of workload utilization and use that to influence the decision.

· Use this policy to mitigate false requests for higher bandwidth and glitches of initial in-rush of commands.

    In a SMP-based system, it was completely observed that the traffic in the physical links that connects multiple chips together are mainly a function of the protocol requests and data transfers that are happening over the link. Different combination of chips and fabric topology gives rise to 1-hop, 2-hop, and 3-hop systems, which determines the complexity of the system and thereby defines the performance of the system. Low-range systems to high-range systems support various levels of data hopping in order to reach to a memory that is present in a remote CPU.

    In order for a CPU to reach the memory behind a different CPU, if there is a direct connect between them, then they just go over the link and get the...