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Method and Structure to reduce Leakage for ESD Device

IP.com Disclosure Number: IPCOM000243998D
Publication Date: 2015-Nov-04
Document File: 1 page(s) / 40K

Publishing Venue

The IP.com Prior Art Database

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Title

Method and Structure to reduce Leakage for ESD Device

Abstract

Disclosed is a method to create a special electrostatic discharge (ESD) macro, which replaces traditional ESD macros, in order to reduce leakage. The approach applies negative voltage bias to reset the ESD macro and a high voltage macro to induce a voltage shift in high K dielectric.

Problem

Current electrostatic discharge (ESD) macros use significant semiconductor product area. A method is needed to reduce the leakage due to ESD structures on a product, especially voltage islands. A new method can improve the lifetime of semiconductor products.

Solution/Novel Contribution

The novel solution is to create a special ESD macro and design product (i.e. wafer/module/system) including those macros. The approach applies negative voltage bias to reset the ESD macro. The approach applies a high voltage macro to induce a voltage shift in high K dielectric.

Method/Process

The new method is meant to replace traditional ESD macros. It uses the same or a little more area than current methods, but reduces leakage. The macro can be reset to the original ESD Field Effect Transistor (FET) characteristic.

Figure: Basic idea

Advantages over Previous Solutions

This solution enables the application of a structure with same capability using less space. It reduces the area required, which reduces product cost.