Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Varactor With Improved Tuning Range in Metal Gate CMOS

IP.com Disclosure Number: IPCOM000244043D
Publication Date: 2015-Nov-09

Publishing Venue

The IP.com Prior Art Database

Abstract

This disclosure describes a varactor with improved tuning range in metal gate CMOS

This text was extracted from a Microsoft PowerPoint presentation.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 42% of the total text.

Slide 1 of 24

Varactor With Improved Tuning Range in Metal Gate CMOS


Slide 2 of 24

Introduction

Doped polysilicon has been used as the gate material in CMOS technology for decades

However, doped polysilicon becomes depleted, degrading transistor performance

  Down scaling of device dimensions increases gate resistance

Metal gate process with high-k dielectric has been introduced at 28nm as replacement for poly gate

Metal Gate

poly

High-k

oxide

P-well

N+

N+

P-well

N+

N+

High-k Metal Gate MOSFET

Poly-Oxide MOSFET

2


Slide 3 of 24

Problem: Varactors Have a Limited Tuning Range

LC-tank frequency tuning range is limited by the varactor

The tuning range of a varactor is from Cmin to Cmax

  Cmax is determined by Cox in accumulation mode, and usually is fixed in a particular technology

  Cmin is mainly determined by the well depletion capacitance (Cdep)

Accumulation-mode varactor

LC-VCO

C-V curve of accumulation-mode varactor

3

[This slide contains 3 pictures or other non-text objects]


Slide 4 of 24

Prior Art

Accumulation-mode varactors have been widely adopted as the capacitance tuning device in LC-tanks

Varactors are “free” in a CMOS fabrication process (No additional steps or masks are required)

However, the tuning range is limited by Cox and Cdep

4

[This slide contains 1 picture or other non-text object]


Slide 5 of 24

Prior Art (Cont…)

Ref [1] shows that when a P+ poly gate is used for the accumulation-mode varactor Cmin can be reduced to improve the tuning range

However, in a high-k metal gate (HKMG) process the poly gate is replaced by a metal gate so the tuning range improvement using P+ poly gate doping in Ref[1] is not possible

  Prior Art is fabricated in 0.12um CMOS technology

  Poly doping concentration used is not mentioned in the paper

[1] J. Maget, M. Tiebout, R. Kraus, “Influence of the MOS varactor gate doping on the performance of a 2.7GHz-4GHz LC-VCO in standard digital 0.12um CMOS technology,” Solid-State Circuits Conf, 2002

From Ref[1]

5

[This slide contains 1 picture or other non-text object]


Slide 6 of 24

Invention

An enhanced tuning range poly-gate varactor in a metal gate (HKMG) process

  Poly depleted capacitance further reduce Cmin of varactor

  Low poly doping concentration minimizes the poly depletion capacitance

  Only one extra mask is needed to keep the poly gate for the varactor

Metal Gate

P+ poly

High-k

oxide

Nwell

P-well

N+

N+

N+

N+

New poly-oxide varactor

NMOS transistor

High-k Metal Gate CMOS Process

6


Slide 7 of 24

P+ Poly-Gate Varactor

Gnd

Vcc

Poly is depleted

Well is depleted

Vcc

Gnd

Vcc

Gnd

P+ poly

oxide

oxide

Nwell

P-well

N+

N+

P-well

N+

N+

Nwell

Depletion

Accumulation

Cdep (poly)

Equivalent Circuit Model

Cox

Cox

Cdep (well)

In accumulation, Cmax ≈ Cox

In depletion, Cmin ≈ Cdep / 2 if poly and well depletion capacitance are almost equal

7


Slide 8 of 24

Poly Depletion Capacitance Estimation (1)

Assume W = 0.36u, L = 0.18u, m = 36, thick oxide

  Cmin of accumulation-mode varactor is ~12fF

  Using the following equatio...