Enhanced Deep Sleep Save and Restore
Publication Date: 2015-Nov-12
The IP.com Prior Art Database
For the past several years the ASIC industry has been working together to define or standardize custom low power designs to reduce implementation and verification efforts The end goal is to submit the behavior of various power features to power format consortium or if not then align the hardware to an existing power format or feature that is standardized already This paper discusses a hardware state retention power gating cell design that complies with existing power formats
For the past several years, the ASIC industry has been working together to define or standardize custom low power designs to reduce implementation and verification efforts. The end goal is to submit the behavior of various power features to power format consortium or if not, then align the hardware to an existing power format or feature that is standardized already. This paper discusses a hardware state retention power gating cell design that complies with existing power formats.
In modern low power, high performance microprocessors, static power is usually defined as the power consumed by the device when it is in quiescent mode, usually implemented as some kind of sleep mode. This is achieved by disabling all activity on the SOC. The only way to save static power is to remove the power supply from the module/segment that is not operational or is not required to be powered on. This additional saving mode in static power out of Sleep mode is referred to as Deep Sleep mode. This is one of the most effective techniques to reduce leakage power in Sleep mode. With this approach the programming contents stored in registers or memory devices may be lost and reprogramming is required, which increases wake up time from Deep Sleep mode before system is ready for use. Of the various techniques that offers recovery of data, which includes reprogramming, one of the effective techniques is to save data in another retention latch running on always on power supply within the flip-flop design thus introducing save and restore function in the register or the flop design. These flops are referred to as a state retention power gating cells. Using this technique, master/slave data is stored in another retention latch before Deep Sleep and recovered from the latch after Deep Sleep. This is the fastest hardware mechanism for resuming to application ready state or operation if entered in to Deep Sleep mode.
Retention cells are also referred to as State Retention Power Gating cell or SRPG cells. These cells are capable of reducing static power used by master or slave or both latches that are connected to switchable power that can be removed. IP or system level verification will may use various power formats that can be integrated with simulators that will emulate the effect of disabling switchable power in simulation when application enters Deep Sleep mode and enabling of power at the exit of Deep Sleep mode.
Gate models of SRPG cells are defined using master and slave latches with retention latch (design dependent), while in RTL an SRPG cell is just a register definition, working on either rising edge or fall edge with level reset definition. When data is saved or restored in g...