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Metal ECO independent ATPG solution

IP.com Disclosure Number: IPCOM000244133D
Publication Date: 2015-Nov-12
Document File: 3 page(s) / 94K

Publishing Venue

The IP.com Prior Art Database

Abstract

This document describes a circuit to mask the impact of design changes on scan ATPG LBIST Problem StatementWith each new revision change however small in most cases it requires a whole DFT and TE PE cycle in terms of ATPG pattern generation and verification LBIST MISR generation and verification and pattern conversion and verification at TE PE end This leads to high utilization of resources both in terms of man hours and compute resources even though the logic changes may be miniscule This has direct impact on schedule as DFT patterns are tape out gating

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Metal ECO independent ATPG solution

Introduction

This document describes a circuit to mask the impact of design changes on scan (ATPG/LBIST).

Problem Statement

With each new revision/change however small, in most cases it requires a whole DFT and TE/PE cycle in terms of ATPG pattern generation and verification, LBIST MISR generation and verification and pattern conversion and verification at TE/PE end. This leads to high utilization of resources both in terms of man-hours and compute resources, even though the logic changes may be miniscule. This has direct impact on schedule as DFT patterns are tape-out gating.

Proposed Solution

A circuit is added comprising a programmable register that holds its value during scan (both ATPG and LBIST). The output is used as a mode signal and it is routed to each hard partition during the initial stages (before logic freeze) of placement and route cycle.  The hierarchical levels to which this signal is routed depends on the size and complexity of design. This mode signal will be utilized in making all dft-cycle impacting change requests transparent in scan modes (ATPG/LBIST).  Hence the current ATPG patterns and LBIST MISR will remain unchanged.  A direct benefit of using this approach is that the circuit has no timing requirement, so its impact on the overall feasibility of the ECO is very low/negligible.

A sample circuit is shown with this implementation:

Original Implementation:

Changed Implementation:

Implementation with the proposed...