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Power-efficient processing of applications involving regular access and processing patterns.

IP.com Disclosure Number: IPCOM000244280D
Publication Date: 2015-Nov-30
Document File: 2 page(s) / 51K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method for efficiently processing workloads having very regular data access and processing patterns

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Power-

-efficient processing of applications involving regular access and processing

     efficient processing of applications involving regular access and processing patterns.

Disclosed is a method for constructing a (power-)efficient processing architecture for processing workloads

involving regular access and processing patterns, such as matrix multiplication, FFTs and other types of linear

algebra applications that are important to many HPC and Big data workloads.

    Typical operation of a conventional general-purpose processor involves the fetching of an instruction vector,

decoding it to determine the source operands, fetching those source operands from the register file at the

offsets indicated in the instruction vector (or fetching data from main memory at the address indicated directly

or indirectly in the instruction vector), which is then followed by executing the operation specified by the

instruction vector and writing back the results. The register file in a conventional processor is typically based

on a multi-port SRAM or similar technology, allowing to fetch multiple operand values in parallel.

These multi-port capabilities, however, come at substantial costs (power and area) compared to a single-port SRAM.

    The disclosed method involves a processing architecture that handles workloads that include very regular

access and processing properties in a more efficient way than a conventional processor. This processing

architecture is illustrated in Figure 1 and is based on the following four aspects.

    The first aspect involves the organization of the register file as multiple single-port...