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Fabrication Method for Hybrid Orientation Vertically Stacked III-V and Ge Gate-All-Around CMOS

IP.com Disclosure Number: IPCOM000244332D
Publication Date: 2015-Dec-02
Document File: 7 page(s) / 332K

Publishing Venue

The IP.com Prior Art Database

Abstract

A fabrication method is disclosed for hybrid orientation vertically stacked III-V and GE Gate-All-Around CMOS.

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Page 01 of 7

Fabrication Method for Hybrid Orientation Vertically Stacked III - Gate- -All

All-

-Around CMOS

Around CMOS

High mobility III-V and Ge are attractive for 5nm CMOS in a gate all around structures. For integration of III-V on Si substrate, growth on Si {111} surface have shown promises. On the other hand, growth of Ge on {111} orientation is very slow, defective and difficult. As a result, hybrid orientation stacked nanowire featuring III-V nanowires grown on {111} and Ge grown on {110} is desired.

Disclosed is a gate-all-around nanowire CMOS fabrication method and structure featuring:

• Stacked III-V nanowires grown on {111} planes • Stacked Ge grown on {110} planes
• The flow requires hybrid orientation substrate, with (110) surface SOI and (100)

standard substrate


The fabrication steps are illustrated with following figures:
The fabrication starts with HOT SOI Substrate, P++ dope the SOI as shown in fig. 1.

Fig. 1

N-FET P-FET STI as shown in fig. 2.

Fig. 2


Mask (110) region, etch Si and BOX, epitaxy (100) Si from substrate seed as shown in fig. 3.

-V and Ge

V and Ge

1


Page 02 of 7

Fig. 3

Fig. 4


HM formation, dummy Fin pattern for both N and P regions as shown in fig . 5.

Fig. 5

Fill Isolation oxide, CMP as shown in fig. 6.

Fig. 6

Recess and dummy fin reveal as illustrated in fig. 7.

Remove STI as shown in fig. 4.

2


Page 03 of 7

Fig. 7

Fill and CMP second dielectric as shown in fig. 8

Fig. 8

Recess second dielectric as illustrated in fig. 9.

Fig. 9


Fill and...