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Oscillator with Comparator Propagation Delay and Input Offset Voltage Compensation

IP.com Disclosure Number: IPCOM000244350D
Publication Date: 2015-Dec-03
Document File: 6 page(s) / 590K

Publishing Venue

The IP.com Prior Art Database

Abstract

Oscillator with Comparator Propagation Delay and Input Offset Voltage Compensation

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Oscillator with Comparator Propagation Delay and Input Offset Voltage Compensation

Introduction

Dual-slope RC oscillators are very often used in integrated circuits for generation of clock signals. Advantage of these oscillators is that they are simple, relatively small and consume low current. One of the main disadvantages of these oscillators is temperature dependency of the output frequency. One source of the temperature dependency is temperature dependency of used resistors, which can be minimized by using resistors with low temperature coefficients. Used comparators are another source of temperature dependency; propagation delay of the comparators is dependent on temperature and plays a significant role for high-frequency oscillators. Temperature dependency of input offset voltage of the comparators is influencing the temperature stability of the output frequency.

The presented solution uses a simple compensation of the propagation delay and input offset voltage of used comparators in dual-slope RC oscillators. The current for charging the timing capacitors is generated from the voltage extracted from the timing capacitors when the comparators trigger; this voltage includes the comparator input offset voltage and propagation delay.

Classical dual slope oscillator

A simplified schematic of a classical dual-slope oscillator is shown in Figure 1. In this type of oscillator, one of the timing capacitors is charged, while the other one is kept discharged. The charging current is generated by placing a reference voltage Vref across a reference resistance R (as hinted by the fraction in Figure 1).

Figure 1: Classical dual-slope oscillator

The oscillator works as follows (Figure 2).

1. Assume the second comparator CMP1 has already triggered. The first half-period of the operation of the oscillator is as follows.


• The output (CLK) signal of the oscillator is logical 0.

1


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• The charging current Ic flows (c0 = 1, d0 = 0) into the first timing capacitor C0; the voltage v0 across it grows linearly.


• The second timing capacitor C1 is kept discharged (c0 = 0, d1 = 1).

• When the voltage v0 across the first timing capacitor C0 becomes high enough, the first comparator CMP0 is triggered, ending the first half-period.


2. The second half-period of the operation of the oscillator follows after the first one.


• The output (CLK) signal of the oscillator is logical 1.

• The charging current Ic flows (c1 = 1, d1 = 0) into the second timing capacitor C1; the voltage v1 across it grows linearly.


• The first timing capacitors C0 is kept discharged (c0 = 0, d0 = 1).

• When the voltage v1 across the first timing capacitor C1 becomes high enough, the second comparator CMP1 is triggered, ending the second half-period.


3. After the second one, the operation of the oscillator returns to the first half-period.

From this point (unless stated otherwise), it will be assumed the comparators are identical (i.e. having same input off...