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Optimized Formal CSI Identification Flow

IP.com Disclosure Number: IPCOM000244355D
Publication Date: 2015-Dec-04
Document File: 6 page(s) / 325K

Publishing Venue

The IP.com Prior Art Database

Abstract

In SOC design, formal method is used to partition SRPG (state-retained power gated) flip-flops to CSI (clock-state independent) flops and non-CSI flops through analyzing clock status in RTL model. Some flops cannot match the clock status requirement and they are included to CSI list, but they have no state retention risk in low power mode, so they need to continue to analyze whether they can be moved to non-CSI flops list to save more area and power, for CSI flops are larger in size and consume more power. This paper uses formal method further checking their Q status of these CSI flops to improve current flow.

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Optimized Formal CSI Identification Flow

ABSTRACT

In SOC design, formal method is used to partition SRPG (state-retained power gated) flip-flops to CSI (clock-state independent) flops and non-CSI flops through analyzing clock status in RTL model. Some flops cannot match the clock status requirement and they are included to CSI list, but they have no state retention risk in low power mode, so they need to continue to analyze whether they can be moved to non-CSI flops list to save more area and power, for CSI flops are larger in size and consume more power. This paper uses formal method further checking their Q status of these CSI flops to improve current flow.

KEYWORDS

SRPG, Formal, CSI, Assertions, SVA, Low-Power

1.     INTRODUCTION

 For SOC design, formal method has been used to partition SRPG flip-flops to CSI flops and non-CSI flops based on analyzing clock status in RTL model. If one flop clock toggle, keep high for positive edge flop or keep low for negative edge flop in low power mode, it referred to as a CSI flops, otherwise those flops which don’t match this condition are non-CSI flops.

There is one kind of flops, their Q or D are not changed during low power, If use current flow, it will be included into CSI list. But through analysis, some of them can be moved to non-CSI list.

2.     MOTIVATION

Fig 1 shows the CSI flow that used in many projects before and currently.

a)      Based on RTL design, scripts and formal tool, get the assertion for each clock, these assertion  check the clock status in low power mode, generally  the assertion check clock low for positive edge flop and check low for negative edge flop ;

b)      Based on RTL design and assertions, the formal tool reports the results for each assertion;

c)       Based on the assertion results and scripts, get the CSI and non-CSI flop lists.

The problem comes: in current flow, there is one kind of flops, their clocks don’t match the assertion condition and it will be included into CSI list. But their Q or D are not changed during low power mode,  through analysis, some of them can be moved to non-CSI list to save more area and power, for CSI flops are larger in size and consume more power.

Fig 1. Previous CSI/non-CSI design flow

3.     Solution.

In order to resolve the above problem, authors develop one new improved flow.

Fig 2 shows the new flow and the improved part is marked with orange color.

a)      Same to the step in 2.0;

b)      Same to the step in 2.0;

c)       Same to the step in 2.0;

d)      When we get CSI list in c) step andsome flops’ information. We can use these CSI reports and some scripts to generate assertions for all the CSI flops, then run formal again...