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Method and system for validating mixed signal connectivity in analog mixed signal design

IP.com Disclosure Number: IPCOM000244357D
Publication Date: 2015-Dec-04
Document File: 6 page(s) / 239K

Publishing Venue

The IP.com Prior Art Database

Abstract

As the size and complexity of analog portion on chip increases, it is becoming more challenging to verify the mixed signal design functions. As code coverage report tool does not support analog signal coverage checking function, this paper builds an AMS based method for analog interface signal coverage checking in analog IP design.

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Method and system for validating mixed signal connectivity in analog mixed signal design

Abstract

As the size and complexity of analog portion on chip increases, it is becoming more challenging to verify the mixed signal design functions. As code coverage report tool does not support analog signal coverage checking function, this paper builds an AMS based method for analog interface signal coverage checking in analog IP design.

Introduction

  Mixed-signal design becomes more and more popular nowadays because designers are required to quickly integrate IPs, control blocks, functional blocks, and analog modules together and run through the design flow to tape out in short time.  Mixed-signal verification turns out to be biggest challenging in mixed signal design. Most of the silicon-respins  could be prevented by better verification methodology.  Among all the big challenges in mixed signal verification, connectivity verification is a main topic these days.

The connectivity verification is focusing on the analog to analog interface or digital to analog interface. Mostly there are three kinds of connectivity errors:

Ø  Inter block communication errors, chicken and egg problems and the like.

Ø  Digital circuitry that controls the analog, produces its input, or processes its output; or it is in the interface between the analog and digital circuitry.

Ø  Complex analog connectivity.

A common method for mixed signal connectivity verification is urgently needed.

  The connectivity issues between Digital and analog circuit may slip through due to insufficient verification. Take Figure 1 for example,  pll_ripple_counter_override_clk is generated inside PLL analog, but it is connected to 0 at top level. Figure 2, the analog IP has three interface signals while only two of them is connecting to digital registers, the third one is tied to 0. Mixed signal verification relies on the behavior model which are verilogAMS model, verilog model or verilogA model mostly, but some functions may not be described in models. Some are not easy to be checked, Figure 3 is a DAC, the buffer function is not described, so the connection between pad and BUF may not be verified.

                  Figure 1.  Mixed signal design connectivity issue1

                  Figure 2.  Mixed signal design connectivity issue2

Figure 3.  Mixed signal design connectivity

  With the complexity of analog design increases, such cases will increase dramatically. There are 300 interface signals for KW40_512 radio analog block, while 240 of them are digital signals.  It is almost impossible to verify 300 interface signal connections with traditional method. Current EDA tools will not directly report analog signal code coverage, a common method for mixed signal connectivity verification is urgently needed to improve design quality.

The method includes below parts:

Ø  Defining one analog IP interface signal connection file (AIP_ICF) which is used to gene...