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An efficient scan test and debug structure for multiple identical cores

IP.com Disclosure Number: IPCOM000244358D
Publication Date: 2015-Dec-04
Document File: 4 page(s) / 77K

Publishing Venue

The IP.com Prior Art Database

Abstract

Today large System-on-Chip (SOC) systems always implemented multiple instances of the identical cores to achieve better performance. During the scan test, , these identical cores will be provided with the same stimulus data and be checked with the same expected data, but they may generate the different response data if there are some defects inside these cores. In current test solutions these features are not considered or fully considered. These solutions will either test these cores serially or perform parallel test by sharing the test stimulus data but with little consideration to the response data. This paper describes a new scan test structure with less test pins and support highly efficient diagnosis.

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                An efficient scan test and debug structure for multiple identical cores

Abstract

Today large System-on-Chip (SOC) systems always implemented multiple instances of the identical cores to achieve better performance. During the scan test, , these identical cores will be provided with the same stimulus data and be checked with the same expected data, but they may generate the different response data if there are some defects inside these cores. In current test solutions these features are not considered or fully considered. These solutions will either test these cores serially or perform parallel test by sharing the test stimulus data but with little consideration to the response data. This paper describes a new scan test structure with less test pins and support highly efficient diagnosis.

Introduction

For identical cores on SOC, traditional scan test methods (serial test or partial parallel test) are not economical and time consuming. A configurable test mechanism could provide more flexibility and perform concurrent subsystem scan test on the very large scale SOC with limited test pin resources.

 The new structure described in this paper, generally, it provides:

1. Less test pin counts to perform parallel scan test on multiple identical cores. The total number of test pins is independent of the number of cores.

2. On chip test observing registers to record the test status of each core, which will save a lot of debug timing efforts.

Design and Implementation

Figure 1 shows the structure of proposed test logic. It consists of two new modules comparing to traditional scan test structure. One is golden core select module and the other is x inhibit compare module. To support such new structure, additional test pins are needed.

Input ‘x_mask_clk’ is a fast clock comparing to scan shift clock, it works as the clock of shift mask value.

Input ‘x_mask’ is a group of mask value inputs. The bit width is depending on the mask clock frequency and the number of scan channel output. It is used to provide information of masking values at every test comparing cycle.

e.g.

If the scan shift clock frequency is 25 MHz, x mask clock frequency is 100 MHz and the number of scan channel out is 100, then the width of x_mask should be 25. 

The information of X mask bit is embedded in the scan test patterns. The X mask bit stream can be easily got by post analyzing the scan test patterns.          

e.g.

 If the expected value in wgl file is as below:

     X00000000X0000000000000000000X10011000001011010001

Th...