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Backside Cooling Vias for SRB Technology

IP.com Disclosure Number: IPCOM000244426D
Publication Date: 2015-Dec-10
Document File: 5 page(s) / 168K

Publishing Venue

The IP.com Prior Art Database


Disclosed is a backside vias based structure to enhance cooling of Strain relaxed buffer (SRB).

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

Page 01 of 5

Backside Cooling Vias for SRB Technology

Disclosed is a backside vias based structure to enhance cooling of Strain relaxed buffer (SRB).

To begin with, a standard SRB IC is formed with a marker layer placed within the SRB layer about 200 nm from the top of SRB as shown in fig. 1. The marker layers can be introduced during SRB epi OR via an implant and can be chosen from the elements such as S, Sn, Sb, In, Ga and Cl.

Figure 1

Moving on, as illustrated in fig. 2, the completed wafer is attached to a handler wafer or an interposer. The wafer can be either whole or diced.


Page 02 of 5

Figure 2

At the next step, backside is ground to a desired length and a block mask is disposed using 1x litho and 1 um resolution with back to front alignment. Thereafter, vias are etched through the substrate and SRB so as to stop on the marker layer as illustrated in fig. 3.


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Figure 3

As illustrated in fig. 4, the vias are filled with TSV like Cu process including Cu barrier, Cu plating and Cu CMP.


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Figure 4

Finally, as shown in fig. 5, the IC structure is completed with substrate heat sink and optional heat sink.


Page 05 of 5

Figure 5

Pattern density of backside "cooling" vias (BCV) can be uniform or can align with particular sensitive areas within the layout. For instance, align dense BCVs with microprocessor cores that tend to have much higher heating and align a lower density BCV's (including none) with memory that require much less cooling.