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Vertical Single Electron Transistor

IP.com Disclosure Number: IPCOM000244464D
Publication Date: 2015-Dec-14
Document File: 4 page(s) / 61K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method and structure for forming an array of vertical Single Electron Transistors (SETs) with uniform SET island sizes and a tunnel barrier

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Vertical Single Electron Transistor

The Single Electron Transistor (SET) is being researched as a potential device option beyond the conventional Complementary Metal Oxide Semiconductor (CMOS). The applications of SET include the supersensitive electrometer , single-electron spectroscopy, an infrared radiation detector, thermometer, memory, etc. The SET characteristics strongly depend on the uniformity of the SET island size and the tunnel barrier. To render the SET a viable option beyond CMOS, it is critical to fabricate the SET so it is compatible with the mature CMOS processing. The desired properties of the SET are smaller islands.

Figure 1: SET schematic

The novel contribution is a method and structure for forming a vertical SET with uniform SET island sizes and a tunnel barrier.

Figure 2 shows a verical single electron transitor All SETs are formed by CMOS process. The uniform
Silicon (Si) island size is controlled by deposition in conjunction of advanced semiconductor patterning, so can 10nm x 10nm or even smaller. The tunnel barrier between source/drain and island can be a low-k dielectric to reduce the capacitance and thus improves the SET sensitivity.

Figure 2: vertical single electron transistor

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The following figures represent the process flow for producing the vertical SET .

Figure 3: Start with Silicon on Isolator (SOI)

Figure 4: Deposit silicon (Si)/dielectric (e.g., SiO2)/Si/SiO2/Si

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Figure 5: Pattern the stack into fin...