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On-chip IO Test Without Physical Contact

IP.com Disclosure Number: IPCOM000244491D
Publication Date: 2015-Dec-16
Document File: 5 page(s) / 403K

Publishing Venue

The IP.com Prior Art Database

Abstract

The number of pads on semiconductor devices has increased greatly over the years. However, due to limited test channels and test cost pressures, not all pads can be contacted by ATE, and the unconnected pads can't be covered during test. On the other hand, it's required that test parallelism should be increased to reduce test cost, which results in more unconnected pads. Thus, there is a potential that some CQIs related IOs will be issued by customers if the unconnected pads aren't tested carefully. Here a test structure and corresponding method are offered to alleviate these issues and reduce test cost.

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On-chip IO Test Without Physical Contact

Abstract:

       The number of pads on semiconductor devices has increased greatly over the years.  However, due to limited test channels and test cost pressures, not all pads can be contacted by ATE, and the unconnected pads can’t be covered during test.  On the other hand, it’s required that test parallelism should be increased to reduce test cost, which results in more unconnected pads.  Thus, there is a potential that some CQIs related IOs will be issued by customers if the unconnected pads aren’t tested carefully.  Here a test structure and corresponding method are offered to alleviate these issues and reduce test cost.

Background

       As chip density and pin numbers increase, to reduce test cost, traditional test method is to probe a minimum number of the pads during probe test so that high parallelism test can be run to reduce test time, and at final test each pin will be tested completely with one test channel for each pin to provide high test coverage. This method has two major problems:

       1. As only minimum pads is tested during probe, defects on other pads will be escaped during probe test, which either causes unnecessary assembly and package cost for the defect parts, or the defect parts are shipped out;

       2. At final test, as all pins will be tested with dedicated test channel. This highly limited the test parallelism in final test, which results in high test cost.

        Actually, with modern DFT technologies (e.g., scan/LBIST, MBIST, Analog BIST/on chip test, etc.),  we can achieve very high test coverage for internal chip logic with a limited number of test pins.  The bottle neck of improving test parallelism is on the IO test, as each pin needs a dedicated test channel with current IO test method.

       It would be better if IC products can be tested fully, including IO functions, but still keep test cost low, which would increase the products’ competiveness.  In this article, an effective test method and apparatus is offered to IO test, which can reduce the contacted pad numbers and cover almost IO test feature. The detailed test structure and related test method will be introduced in the following four sections.

1.   Proposed design test structure

To cover unconnected pads test, it’s required to improve the observability of these unconnected pads with easy control.  Based on the previous principle, one general test structure is proposed in Fig. 1.  From the figure, some main elements are listed here:

      1. In each IO pad, a transmission gate is added to connect pad signal to a common pad test bus under control of ipp_bus_en signal;

      2. The common pad test bus is connected to on chip DAC under control of pad_force_en signal, so that when enabled, DAC can force a desired voltage to each pad to test pad input path(e.g. VIH/VIL);

           3. The  common pad test bus is connected to on chip ...