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Improved Spacer for Nano Sheet Transistors

IP.com Disclosure Number: IPCOM000244655D
Publication Date: 2016-Jan-05
Document File: 4 page(s) / 70K

Publishing Venue

The IP.com Prior Art Database


The disclosure is a method and structure for forming inner spacers for a nanowire/nanosheet MOSFET.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 97% of the total text.

Page 01 of 4

Improved Spacer for Nano Sheet Transistors

A typical nanowire/nanosheet transistor has multiple vertically-stacked horizontal nanowires (nanosheets) as the channel. The conventional spacers clad over the nanowire/nanosheet stack at the spacer region. The inner spacers replace the semiconductor materials between channel nanowires (nanosheets) at the spacer region which can largely reduce the gate capacitances for a nanowire/nanosheet MOSFET. The disclosure teaches a method and structure of forming inner spacers for a nanowire/nanosheet MOSFET. Please see Figures 1 to 6 for the method and structure. The materials used in the Figures are just for example purpose, alternative materials may also apply.

Figure 1: Grow alternative SiGe & Si layers on the substrate (SOI or bulk). Then form fins with the stacked materials.

Figure 2: Form dummy gate and cladding spacers on the fins


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Figure 3: Coat the structure with interlayer dielectric; planarize using CMP which stops on top of the dummy gate; and then selectively remove the original cladding spacers.

Figure 4: Selectively remove SiGe at the spacer region.


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Figure 5: Deposit a spacer material (dielectric) conformally at the spacer region which seals the gaps as shown in Figure 4 and forms the inner spacers. The same dielectric material also forms the cladding spacers.

Figure 6: Remove the interlayer dielectric and continue the following processing


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