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Optimal allocation of High resolution timers based on SRAD affinity

IP.com Disclosure Number: IPCOM000244682D
Publication Date: 2016-Jan-06
Document File: 6 page(s) / 107K

Publishing Venue

The IP.com Prior Art Database

Abstract

Applications often require the use of timers to track events. Timers could be low-resolution or high-resolution depending on the real-time requirements of the application. While low-resolution timers are typically rounded off to 10ms, high-resolution timers need to be extremely precise and typically have a very low granularity. High-resolution timers are managed by scheduling clock interrupts to be as close to the target time as possible.

High resolution timers are used majorly in Real time operating systems that have extremely less torelance levels to delays. This publication addresses the affects of high resolution timers in a NUMA (Non-Uniform Memory Access) envirorment where a high resoultion timer node can belong to a CPU from one SRAD (Shared Resource Affinity Domain) and have its memory allocated from another SRAD. It also considers the thread's own home SRAD that created this timer and how the effects of this on the high resolution timer can be mitigated.

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Optimal allocation of High resolution timers based on SRAD affinity

Disclosed is a method that addresses the issue of high resolution which can be subjected to delay in their expiring due to the following reasons:


1. The high resolution timer node is part of a timer linked list on a CPU that is not in the thread's home SRAD.

2. Memory access for the high resolution timer node is far with respect to the the linked list the node is attached to. (Memory is not allocated from high resolution timer node's home SRAD). In NUMA architecture if far memory is accessed, the delay incurred to bring the information from another SRAD for this memory can be more.

This method solves the problem mentioned above by introducing affinity between the timer allocation and the SRAD that the required thread is running on.

Abbreviations used in the description below:

SRAD : Shared Resource Affinity Domain. SRAD is CPU or cores and the associated memory that is directly attached to it.

NUMA: Non Uniform Memory Access

TRB : Timer Resource balancing list. (Notation for Timer linked list data structure)

HOME THREAD SRAD: SRAD where the thread was started and where the thread will keep running most of the time.

HOME TRB/TIMER SRAD: SRAD where the timer node is attached to a timer list of the SRAD's CPU

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(Figure 1) Best case scenario.

The Timer/TRB node of high resolution "T1" timer for T1 thread is
A. In the TRB list of "C1" core/processor HOME SRAD of the Thread T1.
B. Its memory is allocated from the HOME SRAD of the TRB node.

There are two ways to introduce affinity between timer allocation and SRAD.


1. Timer affinity from CPU perspective:


The trb/timer node for the new timer can be part of timer linked list maintained by a CPU which is not in the home SRAD of the thread that requested for the creation of this timer. Affinity can be brought about between the CPU and the thread that requested for this timer to be created.


2. Timer affinity from memory perspective
trb nodes are part of the trb linked list (timer linked list) that are maintained per CPU. Affinity can be brought about between the CPU that maintains this particular timer linked list and the memory where the new timer node on this linked list will be allocated.

As part of the implementation new fields in trb structure need to be introduced to help identify the affinity between the thread, timer node and SRADs:
> Timer home SRAD info ( the SRAD whose CPU the timer is attached to)
> Thread home SRAD info (the SRAD whose CPU is running the thread that requires this timer and where this thread started executing)

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> Timer node memory home SRAD info (the SRAD from where the memory is allocated to the timer node)


1.Timer affinity from CPU perspective:


Two conditions are taken into consideration:
A. During high resolution timer allocation/attachment to a CPU linked list
B. During timer re-balancing


1. A During high resolution timer allocation/attachment to a CPU linked list:
When a...