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A novel pin access strategy to improve routability

IP.com Disclosure Number: IPCOM000244691D
Publication Date: 2016-Jan-06
Document File: 5 page(s) / 145K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to maximize the number of routing segments used by pin access nets and short nets in a routing track which – at the same time - frees up other, neighboring routing tracks for longer distance routing.

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A novel pin access strategy to improve routability


1. Introduction: Congestion is an increasingly important topic in today's design flow (fewer layers are available, more content per square unit, more restrictive design rules). Congestion mainly occurs due to global wires which is called as global congestion, while congestion due to densely populated pins in a circuit row or shorts nets is subject to local congestion. This method provides a novel technique to mitigate local congestion and improves overall routability of the design.

Traditionally, lower layers have been mainly used for pin access. But with the increase in metal cost designers are recommended to route nets with less number of layers. It now becomes necessary to efficiently utilize lower layers on a chip in order to support long distance routing on upper layers. That is, lower layers must be used for medium distance routing, too. It becomes essential to utilize the lower routing metal layer efficiently to meet the routing demand and mitigate congestion.

Prior approaches which address the issue of local congestion are mostly focused on improving the pin geometry to make them easily accessible. This approach [1] evaluates shape of a pin and find all accessible points in it. However it optimizes the pin access for a pin but it does not consider the effect of other pins in the circuit row. One another method [2] provides a solution by making pin more wider so that pin accessibility can be improved. This method also lacks in optimizing the pin access solution for a whole circuit row.

Pin access routes are usually very short and cause local hot spots within a global tile.Our method solves this problem using a better track optimization technique for short nets and nets used in pin access. This helps in mitigating congestion and also provides more routing tracks to long detail routes and also increases capacity of global edges.


2. Overview and Description: This method solves the pin accessibility issue for each global tile, thus directly helps for better global routing optimizations. As most of the circuit row pins remain on M1 layer, so in this application pin accessibility method only works for M2 layer. However this solution is not limited to only M2 layer and can be easily extended to other metal layers.

This approach works in different steps in the routing flow as shown in fig 1. A horizontal sweep line traverses step-wise through M2 tracks within the boundaries of a given circuit row, resulting in intersection area with M1 pins. For each intersection of M2 cut line and M1 pin, a pin score is computed. The higher this value, the more attractive pin access from M2 down to this part of the M1 pin is.For each track in a global routing tile, a total cut line score (track score) is computed based on the individual pin scores and the total number of pins in that track. A limited number of best routing tracks is selected for short net routes and pin access routes. Penalty cos...