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Method to control hardware simulation errors at run-time with user defined parameters

IP.com Disclosure Number: IPCOM000244704D
Publication Date: 2016-Jan-06
Document File: 5 page(s) / 90K

Publishing Venue

The IP.com Prior Art Database

Abstract

This document details a method to control hardware simulation errors at run time with user defined parameters and actions.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 35% of the total text.

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Method to control hardware simulation errors at run -time with user defined parameters

Cycle simulation and/or verification of microprocessor cores is typically performed at multiple levels such as Block level, Element level and Chip Level, with the verification infrastructure comprising of a design model, a verification test bench which includes user developed components and components provided by the verification methodology, and a simulator. Unit Level simulation is the most accurate with respect to the activity being tracked in the design model per cycle, and typically has full checker functionality enabled in the test bench. At this level of simulation, a multitude of simulation errors can be observed and debugged, since the number of simulated cycles typically ranges in thousands to a few tens of thousands.

But on higher levels of simulation such as Element and Chip, tracking of the design model is typically lower, with test bench checkers being activated only at strategic points in the data flow of the design model. A typical example is for the test bench to only check the architectural state of the processor upon completion of instructions. At these levels, the same checker functionality that is enabled at a lower level such as the unit, may not be enabled. At the same time, the development of the test bench has to take into account the checker functionality required at the most accurate level, assuming that a major portion of the test bench is reused across levels, which is typically desirable.

In such scenarios, higher levels of simulation may prefer in certain cases to reduce the accuracy of the checker functionality of the test bench. One way of doing so would be to temporarily disable checkers that are associated with known design or test bench defects, in order to make forward progress and achieve simulation of a sufficiently large number of cycles typically required at higher simulation levels. Usually, this is done by providing as an input to the simulator, a run-time programmable resource which contains a list of test bench errors to be disabled temporarily.

This disablement of errors can lead to cases where data flow in the design model that is not caught by the checkers can possibly lead to simulation failure not defined by a precise error. One typical example is a simulator watch dog time out, in which case the actual root cause of the time out may not be determined until a detailed debugging of the simulation failure information is undertaken. The effort and time involved in this process typically increases with increasing level of the simulation.

This article describes a method to control simulation errors at run time with user defined parameters and user defined actions that need to be undertaken by the simulator when the conditions based on the parameters are satisfied. The method can be used to do more than just disable checkers as described above, and provides run time programmability and reusability for...