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Criticality based sink redistribution on books with logically transformable multiple outputs

IP.com Disclosure Number: IPCOM000244713D
Publication Date: 2016-Jan-06
Document File: 4 page(s) / 193K

Publishing Venue

The IP.com Prior Art Database

Abstract

This article covers a method to improve the critical path delay originating from cells with multiple output ports, which are logically equivalent or inverse, and have multiple fan-outs where-in only a subset of the fan-outs are timing critical

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Criticality based sink redistribution on books with logically transformable multiple outputs

While technology scaling enables increased device density, it is becoming quite challenging to achieve frequency improvements from one generation to another, due to reduced improvements in device performance and worsening wire-delays. Further, the complexity of designs is increasing with multi-threading, deeper levels of instruction pipelines and larger cone of influence (multiple fan-outs) of control signals in the design. Thus, newer design approaches are required to close timing and improve the frequency of operation.

Typically, design libraries have some logic cells that have multiple outputs that are either logically equivalent or inverse in function, such as latches. Additionally, with the increasing complexity of designs and advancement of tools, the functional interconnectivity of various nets in the designs is greater than before. This manifests itself in a greater percentage of nets in the design having more than one sink with varied degrees of timing criticality. This document presents a method to improve the critical path delays on paths traversing through such cells which have multiple output ports and have multiple fan-outs.

Figure 1 is one example of a multiple-fan-out latch influencing several sinks.

Figure 1 : Example of latches influencing several sinks with varied timing criticality

The path from node An to Bn has a large logic depth and has a negative slack even when all cells in the path are at the lowest VT level - Regular Threshold Voltage (RVT). The path to Cn has a moderate logic depth and has negative slack if all cells are of

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higher threshold voltage (HVT), but it has a positive slack if some of the cells are switched to RVT. The paths to Dn and En have small logic depth and positive slack with all cells being HVT itself.

There are several existing methods to improve critical path delay. Logic restructuring and decomposition and use of better library elements can improve logic depth and reduce path delay. Another method is to switch all cells in the path to the lowest VT level to improve the path delay, which is only possible with an unlimited power - budget constraint, which is not the typical scenario. Also, in this example, Bn is having a negative slack even though all the cells in the path are already at the lowest VT level. In addition to improving the cell delay, wire delay in the path can also be improved to reduce the negative slack. This can be done by several methods such as moving the latch closer to critical sinks, routing the wires to higher metal layers, buffering the long wire delay paths etc....