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Scalable Test Port Architecture

IP.com Disclosure Number: IPCOM000244737D
Publication Date: 2016-Jan-06
Document File: 3 page(s) / 54K

Publishing Venue

The IP.com Prior Art Database

Abstract

Test port is a group of pads connected to chip fabric that can be used to access internal registers or memories using the AHB protocol. Current test port implementations use too many pads. In this paper we present a scalable test port that provides a flexible architecture to perform the complete test port functionalities.

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Scalable Test Port Architecture

[Abstract] Test port is a group of pads connected to chip fabric that can be used to access internal registers or memories using the AHB protocol.  Current test port implementations use too many pads.  In this paper we present a scalable test port that provides a flexible architecture to perform the complete test port functionalities. 

Current test port implementations a direct way to set/read the values of the registers or memories, which makes chip debugging/testing convenient.  However, to communicate with AHB protocol 82 pads are used, which brings following two major problems, (i) design difficulties of pad muxing logic for the chips with same die but different packages, especially the small packages and (ii) pad conflicts when testing different interfaces on ATE.  To solve above issues, scalable test port architecture is developed, which allows the PAD number used for test port is configurable for different packages and even the same package but different test patterns. 

One current implementation of test port is presented as Figure 1 below, on which this scalable test port architecture is based by adding muxes, test port control (TP CONTROL) and configuration registers (CONFIG) shown in Figure 2 (takes half-pad mode as an example).

When 1st half or 2nd half is selected, the original address/control/data/response will be input or output by 2 cycles. The combination of these data will be finished by TP CONTROL.

Figure 1 Current Impl...