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Offline Supported Adaptive Test Methodology

IP.com Disclosure Number: IPCOM000244749D
Publication Date: 2016-Jan-08
Document File: 3 page(s) / 35K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a system to alleviate many of the logistical and procedural hurdles involved with testing a complex semiconductor product in today's mostly fabless world, where speed of change often determines a product’s success in the marketplace. The novel system is a set of adaptive test solutions, provided via a software program-generated chip/site specific execution plan, which enable the application of unique tests or conditions based on previous knowledge.

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Offline Supported Adaptive Test Methodology

Testers of semiconductor products expect the test program to disposition product, from knowingly or questionably defective to optimistically good, into a group of bins. These bins describe whether the tested product is bad or is one of a variety of levels of good. Good product flows from wafer test, through various stages of module test, to system test. At each of these test steps, any changes to the program require a test engineer to code new software, manually insert any new list of chips/wafers for vintage control/special disposition, update any black lists or stop production conditions, perform code review and verification test passes, inspect the analysis of resulting data for potential test software bugs, and so on, for every new change to the test program. This is further complicated by the unique software employed across different test platforms requiring unique code to be written per platform. In addition, at one stage of manufacturing, all these must be kept consistent down through the manufacturing test process (e.g., wafer through module), which again complicated by devices delayed for experimentation or those that come back later.

One existing approach is the use of test programs that go to external resources on the fly to retrieve adaptive solutions for the device under test. Another solution uses test programs written from the beginning for the hardware under test (i.e. in low volume test, a program may be hand-written in a scripting language). Other adaptive solutions are based purely upon the knowledge obtained by the program from the beginning of the test run. Today, because the passing region of test conditions need to be wide enough to allow the expected (allowable) process variation to be observed, the same conditions may allow problematic hardware to unknowingly pass (i.e. an aberration within the limits).

A system or method is needed to fulfill these testing needs without having to move to a contemporary test platform (e.g., one with a high-speed network connection and contemporary processing power) or greatly increasing the software complexity of the test program.

The novel contribution is a set of adaptive test solutions, provided via a software program-generated chip/site specific execution plan, which enable the application of unique tests or conditions based on previous knowledge. The generated execution plan utilizes the known data on this chip/site across its previous test passes to ideally adjust the plan for the next test pass, thus allowing the utilization of many traditional best practices while enabling the benefits of a hand written per-chip per-pass test program. The software program can simulate this execution plan against all possible outcomes through the software flow, in order to best achieve the desired outcome (e.g.,...