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Clock Generator using Comparator

IP.com Disclosure Number: IPCOM000244831D
Publication Date: 2016-Jan-20
Document File: 7 page(s) / 677K

Publishing Venue

The IP.com Prior Art Database

Abstract

A clock generator circuit using a comparator is presented. The circuit uses hysteresis during start-up of the crystal oscillator to remove some spurious frequencies or glitches that may persist for significant periods of time and can result in a poor or unstable clock signal being generated. Once the oscillator is started up and providing a stable oscillating signal, the ratio of hysteresis transistor to mirror transistor is reduced to less than one to disable the hysteresis but maintain the benefit of positive feedback. Disabling the hysteresis in the comparator results in a low phase noise, low jitter clock signal.

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Clock Generator using Comparator

Abstract

A clock generator circuit using a comparator is presented.  The circuit uses hysteresis during start-up of the crystal oscillator to remove some spurious frequencies or glitches that may persist for significant periods of time and can result in a poor or unstable clock signal being generated. Once the oscillator is started up and providing a stable oscillating signal, the ratio of hysteresis transistor to mirror transistor is reduced to less than one to disable the hysteresis but maintain the benefit of positive feedback. Disabling the hysteresis in the comparator results in a low phase noise, low jitter clock signal.

Introduction

In general, SOCs use crystal oscillators as a primary clock source. The crystal oscillator unit includes one Gm amplifier and an external quartz crystal that is connected between the I/O terminals of the amplifier.  This whole unit generates a sinusoidal signal of desired frequency. This signal goes to a comparator that converts the sinusoidal signal to a rail-to-rail square clock signal.  During startup of the oscillations, there may be some spurious frequencies in the crystal or glitches that can results in a bad clock.  This bad clock, if allowed, may lead to a malfunction of the SOC.  In order to avoid the generation of a bad clock, typically sinusoidal signals generated by the crystal units are filtered to remove small disturbance/noise by using hysteresis in the circuit. However this hysteresis may introduce different signal artifacts, for example it may de-grade the RF performance of the clock (i.e., increase clock jitter), so a balanced approach is required to generate a good clock with good RF performance.

Thus for a good crystal oscillator circuit:

•      Hysteresis is required during the start-up phase of crystal oscillator, while the oscillation amplitude of the crystal oscillator signal is small to filter-out some spurious frequencies/glitches.

•      Once the oscillator is started-up and providing a stable oscillating signal, the hysteresis in the comparator need to be disable to provide low phase noise, low jitter clock signal.

                                   

Proposed Circuit Description

The proposed circuit is shown in Figure 1.

Figure 1 Proposed Clock Generator using Comparator circuit

In the comparator the hysteresis can be realized if the number of transistors connected in positive feedback (M7 and M5, M8 and M6) are more than transistor connected as diode load (M3 and M4).  To realize hysteresis, α + β > 1, switches are introduced in the proposed design, which enables swapping the transistor ratio and eventually enable/disable the hysteresis. In the proposed circuit, swapping has been done in the transistor (M7 and M8). The transistors M3, M4, M5, M6, M7, M8, M9, and M10 are identical in size but can differ in multiple. Also, here multiple are taken in relative ratio.

The proposed circuit during crystal oscillator s...