Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Architecture for Pipelining of Scan Enable

IP.com Disclosure Number: IPCOM000244837D
Publication Date: 2016-Jan-20
Document File: 3 page(s) / 79K

Publishing Venue

The IP.com Prior Art Database

Abstract

One of the fault models employed by DFT testing is transition faults, which are tested through transition delay testing and path delay testing. Transition testing is possible only when testing frequency is the same as functional frequency. The two transition fault testing methodologies in use today are LOC (Launch On capture) and LOS (Launch On Shift).

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Architecture for Pipelining of Scan Enable

Introduction: One of the fault models employed by DFT testing is transition faults, which are tested through transition delay testing and path delay testing. Transition testing is possible only when testing frequency is the same as functional frequency. The two transition fault testing methodologies in use today are LOC (Launch On capture) and LOS (Launch On Shift).

In LOC, scan enable can easily make the transition from high to low, but in LOS, scan enable must be designed to make a transition between two high speed clocks, i.e., scan enable signal must operate at full speed.  This is known to provide better coverage, but with increased test cost.  To get the best of both worlds, a pipelined architecture is used for the scan enable signal, which translates LOC scan enable to LOS scan enable for every clock domain (sort of synchronization with respect to each clock).  This scan enable signal is called pipelined scan enable signal.

Figure 1 shows a generic structure that is widely used for pipelining the scan enable signal, whereas the waveforms depicting generation of the pipelined scan enable signal from a non-pipelined scan enable signal are shown in figure 2.

Figure 1: Scan enable pipelining

Figure 2: generation of pipelined scan enable from non-pipelined scan enable signal

The scan enable (SE) is controlled by an external tester and the pipelined scan enable (PSE) is generated internally and forwarded to all the scan enable pins of flops available in scan chains.  PEN is used to activate pipelining of scan enable.  A low value would disable pipelining of scan enable.  Pipelining of scan enable solves the problem of needing a costly external signal to operate top level scan enable signal at functional speed.  This pipelining can be implemented separately for positive edge-triggered and negative edge-triggered flops for each domain.  For pipelining scan enable, extra logic must be added, which includes a pair of scannable flops, AND gates and O...