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AUTO LINK RECOVERY AND TRANSACTION ALIGNMENT IN SYSTEMS WITH BOUNDARY LESS TRANSACTIONS

IP.com Disclosure Number: IPCOM000244849D
Publication Date: 2016-Jan-22
Document File: 3 page(s) / 191K

Publishing Venue

The IP.com Prior Art Database

Related People

Prashant Ranjan: AUTHOR [+2]

Abstract

A mechanism is presented to establish a CONTROL MARKER between the transmitter and receiver of a serial link protocol which is not running any standard packet based protocols. This method allows an easy and light implementation of hardware to send high speed bits across integrated circuits on a board.

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AUTO LINK RECOVERY AND TRANSACTION ALIGNMENT IN SYSTEMS WITH

BOUNDARY LESS TRANSACTIONS

AUTHORS:

Prashant Ranjan Shadab Nazar

CISCO SYSTEMS, INC.

ABSTRACT

    A mechanism is presented to establish a CONTROL MARKER between the transmitter and receiver of a serial link protocol which is not running any standard packet based protocols. This method allows an easy and light implementation of hardware to send high speed bits across integrated circuits on a board.

DETAILED DESCRIPTION

    In a typical chip-to-chip interconnect, a parallel stream of data is striped into multiple smaller chunks and sent over multiples lanes using high speed serial lanes. As shown in Figure 1 below, each lane has a transmitter (TX), which encodes and serializes the data bits, and a receiver (RX), which de-serializes and decodes the data bits to recover original data bits and format. Every transmitter typically uses some kind of coding technique. One example of a coding technique is 64b/66b encoding.

    Both the TX and RX has a set of Gearboxes (GB) as shown in Fig. 1. GB_1 in TX converts data to 64 bits, GB_2 converts 66 bit data to 20 bits as it interfaces with serializer-deserializer (serdes) macro. Similarly, GB_3 in RX converts 20 bit data from serdes macro to 66 bit data and GB_4 converts 66 bit data to Host/upper layer interface.

    Once the circuit is out of reset, both the TX and RX side are continuously sending stream of bits. As the bit streams goes through the set of Gearboxes, there are residue bits stored in them.

Figure 1

Copyright 2016 Cisco Systems, Inc.

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Lane_0_TX

Lane_N_TX

    If for some reason, the RX side is reset in operation, or if there is some overflow in the pipe somewhere after the GB_1 in pipe, then the TX and RX GB goes out of sync. Due to the residue remaining in GB_1, TX and RX never may align to recover the transmitted data properly without the entire circuit being reset.

    The problem above is solved by sending a COMMA frame in a way that serves tw...