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Implementation of High Performance Command Queuing Engine(CQE) for eMMC Controller

IP.com Disclosure Number: IPCOM000244874D
Publication Date: 2016-Jan-25
Document File: 5 page(s) / 77K

Publishing Venue

The IP.com Prior Art Database

Abstract

Command queue mechanism is used in eMMC chip for write and read task management. To offload SW loading, it requires eMMC host controller to support hardware command queue. In this document, we introduce one type of implementation of efficient and high performance Command Queuing Engine for eMMC controller.

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Implementation of High Performance Command Queuing Engine(CQE) for eMMC Controller

Abstract:Command queue mechanism is used in eMMC chip for write and read task management.  To offload SW loading, it requires eMMC host controller to support hardware command queue.  In this document, we introduce one type of implementation of efficient and high performance Command Queuing Engine for eMMC controller.

1.     Introduction

Command Queuing (CQ) feature is introduced to eMMC standard in v5.1. CQ includes new commands for issuing data transfer tasks to the device for ordering the execution of previously issued tasks, and for additional task management functions. In order to optimally exploit CQ, we have designed Command Queuing Engine(CQE) in eMMC controller.  With CQE, eMMC controller can execute the bus protocol and provide task-level interface to software and software issues tasks to the hardware and is notified when they are completed.

To get maximum performance of eMMC data transfer, CQE should automatically send queuing command and executing command as quickly as possible to avoid unnecessary degradation in performance of eMMC data transfer. So we have designed multiple FIFOs and state machine structures in CQE according to command queue flow’s characteristic.

2. SW Command Queue flow

For one write/read operation, SW command queue need 3 steps.

1.     Queuing a Transaction (CMD44+CMD45)

To queue a data transfer task, the host issues a CMD44 followed by a CMD45. CMD44 encodes the Block Count, Task ID, Data Direction, and Priority. CMD45 encodes the transaction address.

2. Checking the Queue Status (SEND_STATUS - CMD13)

 In order to determine, which tasks are ready for execution, the host can read the Queue Status Register (QSR). In order to read the QSR, the host issues SEND_STATUS

3. Execution of a Queued Task (CMD46/CMD47)

In order to execute a previously queued task, the host issues a CMD46 or a CMD47, encoding the Task ID of the requested task. CMD46 is used for the execution of Read commands, and CMD47 is used for Write commands. The host shall only issue CMD46/CMD47 for tasks, which are shown as “ready for execution” in the QSR.

2. SW + CQE flow

 Below is SW+CQE flow for command queue task execution.  CQE need complete step3~6 in order for one data transfer task.  Then notify SW in step7.         

In this flow, SW do not need participate in every CMD. SW just need prepare descriptors, enable CQE and wait for CQE notification. 

1. SW prepare descriptors.

    The descriptor encodes the Block Count, Data Direction, Priority and all the information for queuing and execution task.  Can enable multiple task at once.

2. SW write CQE register to notify which task ID descriptors are ready.

3. CQE read corresponding descriptor and extract information for queuing and executing CMD.

4. Queuing a Transaction (CMD44+CMD45)

5. Checking the Queue Status (SEND_STATUS - CMD13)

6. Execution of a Queued Task (CMD46/CMD47)

7. Notify SW when...