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Mirrored Contact CMOS with Air Gap

IP.com Disclosure Number: IPCOM000244876D
Publication Date: 2016-Jan-25
Document File: 4 page(s) / 324K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to significantly change the design space of a transistor in a Complimentary Metal-Oxide Semiconductor (CMOS) by moving contacts to the backside, allowing the formation of air gaps on the frontside for additional reduction of PC to source/drain (S/D) capacitance.

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Mirrored Contact CMOS with Air Gap

A Complimentary Metal-Oxide Semiconductor (CMOS) has two primary extrinsic (parasitic) elements that detract from the device/circuit performance: extrinsic capacitance (CA to PC), and Middle-of-Line (MOL) Contact Resistance (CA or CA+TS). Decreasing gate height reduces CA to PC capacitance, but increases gate resistance, thereby impacting performance. Decreasing gate pitch, Contacted Poly Pitch (CPP), scales the device area, but decreases the area for the source/drain (S/D) contact, thereby increasing extrinsic resistance and reducing effective drive current, Leff.

A method is needed to reduce the detrimental impact of scaling on the capacitance and resistance of the S/D.

The novel contribution is a method to significantly change the design space of a transistor by moving contacts to the backside, allowing the formation of air gaps on the frontside for additional reduction of PC to S /D capacitance.

The method mirrors the contacts to the backside of the device and forms air gaps on the front of the device above the S/D. By finishing the device up until (not including) the contacts, flipping and bonding the device, thinning the backside, and making contacts for the source/drain/gate through the backside, significant reduction in capacitance can be achieved and additional room for the contacts obtained . Full air gap is possible above S/D epitaxy (epi).

No current solution exists that benefits both issues.

Figure 1: Mirrored Cont...