Browse Prior Art Database

A High Available Architecture for Supporting multi-sockets Server System

IP.com Disclosure Number: IPCOM000244879D
Publication Date: 2016-Jan-26
Document File: 8 page(s) / 395K

Publishing Venue

The IP.com Prior Art Database

Abstract

The core idea of this enhanced multi-sockets architect is to define the balanced role for all the sockets and make the Master Socket selectable. Thus, when the system stop booting due to the Master’s issue, the new Master can be selected by BMC to boot the system. It is a mux based architecture including hardware and corresponding firmware for multi-sockets system to support dynamic switch of master socket, boot path and error log/recovery channel to achieve high available system.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 53% of the total text.

Page 01 of 8

A High Available Architecture for Supporting multi

A High Available Architecture for Supporting multi-

--sockets Server System

sockets Server System

The below Figure 1-1 shows the current typical 4-Sockets system architect. The CPU0, who have the direct LPC connection with BMC, is the Master processor. All the other three are the slave processor. When BMC send magic code to CPU0 via Service Interface (I2C Master Interface in BMC). The CPU0 starts to fetch the BIOS via the direct connect LPC. Then, the Master will trigger start all the Slave processors via its Service Interfaces (SI).

The Master Processor becomes the key point of the system in this kind of architect. It brings the below limitations:

1. The system will stop booting up if any issue happen in Master Processor. For example, the Service Interface down between Master processor and BMC.


2. This system architect cannot support the hardware partition easily.

1


Page 02 of 8

Figure 1-1 Typical 4-Sockets System Architecture

Enhanced System Architecture Summary

The enhanced multi-sockets system architecture tries to give the balanced role for each processors. From the hardware connection level, as shown in below Figure 1-2, all the processors have their LPCs connect together to BMC. And each processor has one Master Service Interface and one Slave Service Interface connect to BMC. BMC have the system control to decide who can be the master. When booting up, BMC will try to bring up Service Interface to the first Master processor and check the processors healthy. If have any problem on Service Interface bring up or the first master not healthy, skip it and

2


Page 03 of 8

try the second master. After the master boot u...