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Method and Apparatus for Delayed Blocking of the Instruction Issue in Microprocessor Following a Pipeline Start-Up to Reduce the Voltage Droop Disclosure Number: IPCOM000244893D
Publication Date: 2016-Jan-27
Document File: 4 page(s) / 156K

Publishing Venue

The Prior Art Database


Disclosed is a method to mitigate voltage droop by delaying the start of the blocking of the instruction issue, which allows the execution to uncover as many long-latency cache misses as possible while running the pipeline at the maximum throughput.

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Method and Apparatus for Delayed Blocking of the Instruction Issue in Microprocessor Following a Pipeline Start -

-Up to Reduce the Voltage Droop

Up to Reduce the Voltage Droop

Modern processors include extensive execution resources to support concurrent processing of multiple instructions. Providing a processor with extensive execution resources requires significant amounts of power for running. Different execution units may consume more or less power and draw more or less current, depending on size and the implemented functions; the net effect of packing so much logic onto a relatively small process chip is to create the potential for significant power supply and power dissipation problems. Few programs require the full range of a processor's execution resources for significant time intervals. The power dissipated running a program depends on the nature of its component instructions and the associated potential to be executed in parallel. Programs typically include a variety of instruction types, but it is rare that enough instructions of the correct type are available to keep all of the processor's execution resources busy for significant periods. For this reason, most processors employ a clock gating mechanism to cut off the clock delivered to execution resources that are not in use. In addition, different components of an execution resource can be turned on and off as instructions enter and exit the pipe stage serviced by the component. Clock gating reduces power consumption, but it can also cause rapid changes in the current provided to the processor. These current changes can alter the voltage at which the processor logic operates.

Clock signals are typically delivered to the processor's execution resources through a clock distribution network. The clock signal is used to synchronize the charging and discharging of nodes in the processor logic between supply voltage levels (e.g., Vcc and ground). The logic is designed to operate within specified ranges of these voltage levels, which are maintained by a regulated power supply. Sudden changes in the current drawn by the processor as functional units are gated on or off can cause these supply voltages to vary. The voltage variations are due to the finite response time of the power supply as well as reactive (inductive and capacitive) elements in the power distribution network. Voltage variations that fall outside the specified range can damage circuits (for voltage excursions above a maximum safe value) or create errors (for voltage excursions below a level necessary to guarantee correct operation of the logic).

The significance of these voltage excursions is determined by the rate at which the current provided to the processor by the power supply changes (i.e., current change rate or di/dt ) and the electrical properties of the distribution network. For processors that implement clock gating, the current change rate depends on both the size of the current change and the time...