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A Method for Fabricating Silicon-Germanium on Insulator Substrates

IP.com Disclosure Number: IPCOM000244936D
Publication Date: 2016-Feb-02
Document File: 4 page(s) / 139K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method of forming high %Ge film on a Silicon-Germanium on Insulator (SGOI) substrate such that the SGOI can be made thick with low defectivity.

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Title

A Method for Fabricating Silicon-Germanium on Insulator Substrates

Abstract

Disclosed is a method of forming high %Ge film on a Silicon-Germanium on Insulator (SGOI) substrate such that the SGOI can be made thick with low defectivity.

Problem

Using a higher percentage (%) Germanium (Ge) Silicon-Germanium (SiGe) films with greater mobility compared to Si, lowers the power consumption and increases switching speeds in Field Effect Transistors (FETs). In addition, the performance benefits of Silicon on Insulator (SOI) and finFETs go beyond acceptance and are demonstrated extensively in practice. It stands only matter of time until a high %Ge SiGe finFET technology on SOI is realized. A well-documented method of achieving Silicon- Germanium on Insulator (SGOI) is through Ge condensation or the thermal extraction and oxidation of Si from a SiGe film.

High %Ge SiGe is being pursued for finFET technologies 7nm and below. Ge condensation is being considered on SOI for rapid fabrication of SGOI substrates. Performing Ge Condensation on full 300mm SOI wafer produces high defect densities due to buried oxide (BOX) warping and dislocation formation. Dislocations can be minimized by limiting the film thickness. High defect densities are never acceptable. Limiting the SGOI thickness can limit the final fin height. Such limitations in fin height limit device performance or can negate expected improvements.

Figure 1: Cross-section of twin defect created by excessive compr...