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Local Wiring below BOX (LWbB) in SOI Technologies

IP.com Disclosure Number: IPCOM000244937D
Publication Date: 2016-Feb-03
Document File: 3 page(s) / 66K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to generate local wiring below buried oxide (BOX) in Semiconductor on Insulator (SOI) technologies (by metal/doping). This method generates local wiring at the interface between a bulk wafer and BOX and creates a contact via Contact Area RECtangle structures (CAREC) along BOX, down to the conducting interface layer.

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Title

Local Wiring below BOX (LWbB) in SOI Technologies

Abstract

Disclosed is a method to generate local wiring below buried oxide (BOX) in Semiconductor on Insulator (SOI) technologies (by metal/doping). This method generates local wiring at the interface between a bulk wafer and BOX and creates a contact via Contact Area RECtangle structures (CAREC) along BOX, down to the conducting interface layer.

Problem

A method is needed to generate a local wiring at the interface between a bulk wafer and buried oxide (BOX) and create contact via Contact Area RECtangle structures (CAREC) along BOX, and down to the conducting interface layer.

Current approaches use wiring on top of a Semiconductor on Insulator (SOI) film. The back gate in bulk material is used for back gating of the device only.

Solution/Novel Contribution

The novel contribution is a method to generate local wiring below buried oxide (BOX) in Semiconductor on Insulator (SOI) technologies (by metal/doping). The method is to make contact from the top of SOI via a CAREC-like process, along the NOSOI etch border. The method includes the option to protect the SOI/BOX sidewall using a spacer along NOSOI or using a SOI sidewall to support the contact. The options for lateral definition include:

• Via active area (RX) etch/deep Shallow Trench Isolation (STI)

• Separate formation mask in Front End of Line (FEOL) flow (e.g., formation by implant)

• Separate mask during wafer manufacturing (i.e. SMART CUT process); possible because only large structures are required as wiring/land pads

Method/Process

The novel solution has two possible embodiments.

The first is an implanted doped layer. For example:
n+ doping in p- substrate [p- substrate is industry standardfor CMOS applications]

The second is to form a conducting layer. For example:

Metal layer/NiSi/Wsix on top of a bulk wafer (formed prior to SMA...