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A Rail to Rail Output Stage with Infinite DC Input Impendence and Improved Large Signal Response

IP.com Disclosure Number: IPCOM000245168D
Publication Date: 2016-Feb-16
Document File: 4 page(s) / 253K

Publishing Venue

The IP.com Prior Art Database

Abstract

A rail-to-rail output stage always limits the bias condition of a former stage. A not well biased former stage will degrade the offset of OTA. Some designs relaxed the bias condition of the former stage with the drawback of output resistance degradation, which decreases the overall DC gain. In this paper we present a design that can relax the bias condition of the former stage without an output resistance decrease and large signal response degradation.

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A Rail to Rail Output Stage with Infinite DC Input Impendence and Improved Large Signal Response

Abstract

A rail-to-rail output stage always limits the bias condition of a former stage.  A not well biased former stage will degrade the offset of OTA.  Some designs relaxed the bias condition of the former stage with the drawback of output resistance degradation, which decreases the overall DC gain.  In this paper we present a design that can relax the bias condition of the former stage without an output resistance decrease and large signal response degradation.

Introduction

Figure 1 shows a conventional and widely used rail-to-rail output stage.  The quiescent current of M6 and M7 is set by floating current source M4 and M5.  The bias part of the circuit M0-M5 is usually merged in the former stage, and M0-M5 is part of the former folded cascode stage.  The Vgs of M6 limits the Vds of M0 and M1.  The same case occurs with M2 and M3.  The limitation makes Vdsat of M0 and M2 much lower than the best value.  Low Vdsat of M0 and M2 makes gm of M0 and M2 much larger, which makes the offset of M0 and M2 contribute strongly to the total OTA input offset.

If the bias part M0-M5 is not merged with the former stage, the bias condition of the former stage would be good, but this would lead to a large signal response problem.  When former stage output voltage decreases, M4 is turned off, which makes the gate of M7 a high resistance node.  M7 gate with high resistance leads to a large phase shift, which can cause stability problems.  If the output of the former stage increases, a similar problem will occur at the gate of M6.

Figure 1. Conventional Rail-to-Rail Output Stage

The motivation of the proposed design is to make the former stage biased at good condition without any large signal response degradation.

 

Design and Implementation

Figure 2 shows the implementation of our proposed output stage circuit.

1.       Quiescent current of output transistors M6, M7 is set by the size ratio between M4 and M6.

2.       The size ratio between M2 and M5 is the same as the size ratio between M3 and M7.

3.       Vin can be connected to output of the former stage. The bias voltage of former stage’s Vdsat can be released to two times of Vgs, which is enough for a folded cascode stage.

4.       The DC input resistance of this output stage is infinite for Vin is the gate of MOSFET M1.

5.       The design has...