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Low Jitter Level Shifter with Dynamically Controlled Logic

IP.com Disclosure Number: IPCOM000245171D
Publication Date: 2016-Feb-16
Document File: 8 page(s) / 1M

Publishing Venue

The IP.com Prior Art Database

Abstract

Level shifters find extensive use in modern day SOCs employing multiple power domains. Most available level-shifter architectures focus on power-efficiency, area-efficiency and high performance (speed). The most overlooked factor is jitter performance. Level-shifters used in IOs in the system clock paths have the basic requirement of low jitter while maintaining reasonably high speeds. In this paper we propose a design that reduces jitter due to core (input) supply noise. The simulation results for 55nm technology show a significant improvement in jitter (due to core supply noise) over conventional designs.

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Low Jitter Level Shifter with Dynamically Controlled Logic

Abstract: Level shifters find extensive use in modern day SOCs employing multiple power domains. Most available level-shifter architectures focus on power-efficiency, area-efficiency and high performance (speed). The most overlooked factor is jitter performance. Level-shifters used in IOs in the system clock paths have the basic requirement of low jitter while maintaining reasonably high speeds.  In this paper we propose a design that reduces jitter due to core (input) supply noise.  The simulation results for 55nm technology show a significant improvement in jitter (due to core supply noise) over conventional designs.

Design: As technology is continuously scaling down, core supply and MOS threshold voltages are also scaling down but threshold voltages don’t have similar scaling down factor.  This limits the pull down capability of NMOS in level shifters.  In conventional level shifters (Fig: 1), when input switches from LOW to HIGH, upper PMOS is ON, which creates the contention path. This slows down the operation, which is reflected as Jitter at the output. This again has a dependency on pull down capability of NMOS.

Additionally, noise in the core supply reduces the pull down capability of driver NMOS, which is again partially attributed to this contention problem, results in poor jitter performance, which is highly unacceptable in high speed links especially in IOs. Thus, there is a need to provide an improved level shifter having optimal jitter performance in high speed links when the core supply is noisy.

Fig 1: Conventional Level Shifter

VDD_H: Higher voltage supply

VDD_L: Lower voltage supply

GND: ground

Out: output of level shifter

Out_b: inverted output of level shifter

The proposed design (Fig: 2) describes a high speed low power level shifter in which the contention path between the driving NMOS and feedback PMOS is avoided by placing a transmission gate whose select inputs are being controlled by dynamic logic.  This increases speed and reduces the jitter.  This also results in getting rid of direct current path from VDDH to GND during transition of OUT and OUT_b, thus reducing power consumption.

Fig 2: Proposed Circuit

Circuit Operation:

In the proposed design, the contention path between the driving NMOS MN1&MN2 (coupled to lower voltage logic inputs) and the PMOS MP2&MP1 (acting as feedback elements) is avoided by placing the transmission gate between them.  These transmission gates act as switches thereby eliminating the current path from supply to ground during transition.  The input of these transmission gates is controlled by 'dynamic logic'.

These intermediat...