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Reliable Self-test of Voltage Monitor Circuits and Self-test State Capturing Protocol

IP.com Disclosure Number: IPCOM000245173D
Publication Date: 2016-Feb-16
Document File: 4 page(s) / 119K

Publishing Venue

The IP.com Prior Art Database

Abstract

In any Power management system, LVDs (Low voltage detectors) and HVDs (High voltage detectors) are used to ensure desired supply is operational within specified operating range. Comparators play a key in LVD/HVD circuit designs so to ensure proper operation of LVD/HVD circuits, it is necessary to test them in silicon. Self-test is a mode where the correctness as well as functionality can be checked internally and its test report is registered digitally without any external resource. This article proposes an accurate self-test architecture that takes care of LVD/HVD's functionality as well as accuracy to ensure its robustness.

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Reliable Self-test of Voltage Monitor Circuits and Self-test State Capturing Protocol

Abstract

In any Power management system, LVDs (Low voltage detectors) and HVDs (High voltage detectors) are used to ensure desired supply is operational within specified operating range.  Comparators play a key in LVD/HVD circuit designs so to ensure proper operation of LVD/HVD circuits, it is necessary to test them in silicon.  Self-test is a mode where the correctness as well as functionality can be checked internally and its test report is registered digitally without any external resource.  This article proposes an accurate self-test architecture that takes care of LVD/HVD’s functionality as well as accuracy to ensure its robustness.

Problem description

The main objective of self-test is to ensure there are no-stuck at faults in LVD/HVD monitors.  To check this the most simple mechanism is to toggle the input of the comparator from high to low and low to high.  The toggling event is captured in a register to check whether proper toggling has occurred.

To do this check, traditionally a large input glitch signal is applied to force the comparator to toggle.  However, in actual applications, the comparator has to respond to a small differential input.  Further, the glitch time may also vary widely.  As a result, in some corner case scenarios, the comparator may not be able to respond within the glitch time, which may yield a false result, so this kind of structure is not good for self-test.

The self-test architecture sometimes involves a signal loop, which may get stuck in some intermediate value resulting in failure of the self-test so a loop less architecture is preferable for fail safe operation.  Further, during exit of self-test, it must return to normal functional operation without disturbing the normal operation.  In some architectures, if the supply remains between high and low threshold (VTH and VTL) and system exits from self-test, then a false reset may occur and normal function is disturbed.  Thus, the architecture must take care of this issue also.

Solution

Figure 1: Block Diagram

Major advant...