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Method and structure for forming FEOL on-chip MIM capacitor

IP.com Disclosure Number: IPCOM000245179D
Publication Date: 2016-Feb-17
Document File: 5 page(s) / 353K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method and structure for forming on-chip capacitors by leveraging the self-aligned contact (SAC), which becomes a critical technology feature for 10nm and beyond.

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Page 01 of 5

Title

Method and structure for forming FEOL on-chip MIM capacitor

Abstract

Disclosed is a method and structure for forming on-chip capacitors by leveraging the self-aligned contact (SAC), which becomes a critical technology feature for 10nm and beyond.

Problem

On-chip capacitors are essential for a variety of semiconductor applications (e.g., System on Chip (SoC)). The conventional on-chip capacitors either use Front-End-of- Line (FEOL) metal-oxide semiconductor (MOS) capacitors or Back-End-of-Line (BEOL) metal-insulator-metal (MIM) capacitors. Each type of capacitor has drawbacks.

Solution/Novel Contribution

The novel contribution is a method and structure for forming on-chip capacitors by leveraging the self-aligned contact (SAC), which becomes a critical technology feature for 10nm and beyond. The inventive capacitors use the dummy metal gates (MG) as one electrode, the SAC contacts as another electrode, and the spacers between MG and SAC as the dielectric.

Method/Process

Embodiment #1: Standard processes forming

1. High-k/metal gates (HKMG) (by gate-first or replacement gate) on active region and isolation region on a substrate (bulk or Silicon on Insulator (SOI))


2. Form inter-layer dielectric (ILD) and an insulator cap on top of the gates

Figure 1: Standard processes forming


3. Deposit second ILD (e.g., oxide)

4. Self-aligned contact (SAC) patterning


Page 02 of 5

Figure 2: Second deposit

5. Fill SAC opening with conductor materials (e.g., Tungsten (W) with...