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A method for Die alignment in 3D stacked dies using reflectometry

IP.com Disclosure Number: IPCOM000245350D
Publication Date: 2016-Mar-02
Document File: 3 page(s) / 133K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to use reflectometry (i.e. time domain or frequency domain) to align dies. This generic approach allows for single ended access with increased sensitivity.

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Title

A method for Die alignment in 3D stacked dies using reflectometry

Abstract

Disclosed is a method to use reflectometry (i.e. time domain or frequency domain) to align dies. This generic approach allows for single ended access with increased sensitivity.

Problem

Proper functioning of a three-dimensional (3D) stack is dependent on proper contact between functional components of the dies in the stack (e.g., Through-Silicon-Vias (TSV) Landing Pads to Bumps, TSV to TSV, etc.), which is dependent on alignment of dies. In addition to the misalignment of dies, the individual components (e.g., ubump) can be misaligned. Failure of proper contact between functional components can lead to failure of the entire stack.

A method is needed such that stacking in 3D integrated circuits (IC) can be tested in an efficient manner during qualification to ensure a quick tape out with a best case scenario or determination of a critical fault. Such a method can ensure good quality and save costs by avoiding failures in field.

Current methods of aligning dies/wafers in a 3D stack are limited in terms of sensitivity.

Solution/Novel Contribution

The novel contribution is a method to use reflectometry (i.e. time domain or frequency domain) to align dies. This generic approach allows for single ended access with increased sensitivity.

Method/Process

The steps for implementing the reflectometry method follow:

1. Z1 and Z2 is impedance of (TSV 1 + Landing Pad) (Top Die) and TSV 2 + (Landi...