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Power Semiconductor Single-Chip Package for Harsh Environments

IP.com Disclosure Number: IPCOM000245373D
Publication Date: 2016-Mar-04
Document File: 6 page(s) / 110K

Publishing Venue

The IP.com Prior Art Database

Related People

Cédric Bessire, Jürgen Schuderer: AUTHOR

Abstract

A chip-level package is proposed that guarantees a protection of HV power semiconductors by a thick, high-strength barrier on the topside to enable superior robustness against contamination, particles and harsh environments even in liquids, in particular with the following features and properties: • New single-chip package for power semiconductor chips with high-field regions around the chip being fully embedded in a solid insulating material. • Bare dies are replaced by chip-level packages that can be handled again as a single chip. Such packaged die are very robust against backend contaminations (particles, residues) and allow for HV test & scrap prior to encapsulation, which can provide a yield benefit. • The chip-level package can be used as a direct assembly solution on coolers or for integration on various module types. New power module solutions such as a pressure- liquid tolerant StakPak for subsea applications, or a direct-immersion cooled power module are enabled.

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04.03.2016

CH-1427501

Power Semiconductor Single‐Chip Package for Harsh Environments 

Authors: C. Bessire, J. Schuderer

TECHNICAL FIELD

The present disclosure describes a new solution of power semiconductor single-chip package for harsh environments.

BACKGROUND OF THE DISCLOSURE

Packaging is essential for semiconductors in order to connect them electrically and protect them from environmental influence. This is in particular the case for power semiconductors that are employed as main switching elements in various applications like frequency converters which are used to drive motors in pumps, compressors etc..

Frequency converters in the medium voltage and high power range drive electric motors by controlling the speed and torque of these machines and are a well proven equipment.

For power semiconductors, several trends, developments and reports give evidence that actual edge termination passivation performance is not sufficient for environmental challenging applications. Improved passivation performance and robustness is needed for: • Operation in novel environments and encapsulations such as dielectric liquids for pressure- tolerant subsea converters or liquids for direct immersion cooling.

• Operation in humid environments, such as for trains operating in humid countries / entering tunnels, etc.

• Improved robustness against particle contamination in production: a general issue and ever present quality concern.

• Wide bandgap semiconductors having intrinsically higher internal E-fields and respective higher edge termination surface field stresses.

• 3D integrated packages and stray inductance minimized packages with higher Junction termination fields due to vertical integration.

SUMMARY

The disclosure provides a chip-level package is proposed that guarantees a protection of HV


Page 02 of 6

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04.03.2016

CH-1427501

power semiconductors by a thick, high-strength barrier on the topside to enable superior robustness against contamination, particles and harsh environments even in liquids, in particular with the following features and properties: • New single-chip package for power semiconductor chips with high-field regions around the chip being fully embedded in a solid insulating material.

• Bare dies are replaced by chip-level packages that can be handled again as a single chip. Such packaged die are very robust against backend contaminations (particles, residues) and allow for HV test & scrap prior to encapsulation, which can provide a yield benefit.

• The chip-level package can be used as a direct assembly solution on coolers or for integration on various module types. New power module solutions such as a pressure-liquid tolerant StakPak for subsea applications, or a direct-immersion cooled power module are enabled.

DETAILED DESCRIPTION OF EMBODIMENTS

A power semiconductor chip, e.g. an IGBT, can be sintered or soldered onto a lead-frame (cavity or plane) as illustrated in Figure 1. The chip on...