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A Method for Providing Split-Gate FinFET for Analog Applications

IP.com Disclosure Number: IPCOM000245405D
Publication Date: 2016-Mar-07
Document File: 3 page(s) / 51K

Publishing Venue

The IP.com Prior Art Database

Abstract

A method is disclosed for splitting a long-channel gate contact into multiple smaller channels in series for analog applications.

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This is the abbreviated version, containing approximately 86% of the total text.

Page 01 of 3

A Method for Providing Split-Gate FinFET for Analog Applications


In general, long-channel devices like NMOS and PMOS are desired for analog applications. The devices exhibit lower noise compared to a short-channel counterpart for a given transconductor efficiency. In addition, the transistor gain is also higher for the long-channel devices.

However, fabrication of long-channel devices in replacement metal-gate process flow is challenging as a CMP process step is usually employed to planarize the various gate-layers. This step leads to variable gate height along with the channel resulting in severe long-channel threshold voltage (Vt) variability. This problem is further exacerbated for state-of-the art trigate devices with self-aligned contact scheme.

Disclosed is a method for splitting a long-channel gate contact into multiple smaller channelsĀ in series for analog applications.

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Page 02 of 3

Fig. 1 and Fig. 2 illustrate a proposed structure in accordance with the method disclosed herein.

Figure 1

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Figure 2

As shown in Fig. 1 and Fig. 2, split-gate device has a plurality of gate contacts in series with each other, each with let's say about 20-100 nm long. This structure prevents gate height variations and provides uniform Vt for long channel devices across the entire wafer.

In accordance with the method, the Vt of the split-gate device is moderately higher let's say about (5-10mV) than a corresponding conventional long channel device. Due to the s...