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Method for Measurement and Modeling of Layout Parasitic for Back Annotation

IP.com Disclosure Number: IPCOM000245409D
Publication Date: 2016-Mar-08
Document File: 5 page(s) / 217K

Publishing Venue

The IP.com Prior Art Database

Abstract

Post-layout simulation of analog blocks (custom layout) with RC extracted netlist suffers from very slow simulation speed due large numbers of parasitics in the extracted netlist. Pre-layout simulation suffers from inaccuracy as actual layout parasitics are not present. Parasitic back annotated schematics are used to achieve optimum trade-offs between speed and simulation accuracy. Here the parasitic measurement can be done using a layout extracted netlist. For back annotation, a simple and accurate model for back annotating net segment's R & C is also required for a good trade-off between the simulation speed and accuracy. In this paper we present a method for parasitic back annotation that is targeted for the trade-off between simulation speed and accuracy

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Page 01 of 5

Method for Measurement and Modeling of Layout Parasitic for Back Annotation

Abstract:

Post-layout simulation of analog blocks (custom layout) with RC extracted netlist suffers from very slow simulation speed due large numbers of parasitics in the extracted netlist. Pre-layout simulation suffers from inaccuracy as actual layout parasitics are not present. Parasitic back annotated schematics are used to achieve optimum trade-offs between speed and simulation accuracy. Here the parasitic measurement can be done using a layout extracted netlist. For back annotation, a simple and accurate model for back annotating net segment's R & C is also required for a good trade-off between the simulation speed and accuracy. In this paper we present a method for parasitic back annotation that is targeted for the trade- off between simulation speed and accuracy

Introduction:

     Parasitic back annotated schematics are used to achieve an optimum trade-off between simulation speed and accuracy to circumvent the speed issues of post-layout RC extracted netlist and inaccuracy pertaining to pre-layout schematic simulation. For accurate and optimum modelling, the net must be bifurcated into multiple segments and modelling must be done for each of the segments. One method therefore is proposed in this paper.

     If a net goes to more than one destination, parasitic capacitance must be measured and back- annotated for each net segment separately. Segments are determined by the bifurcation points. For example, in Fig. 1, there are 3 segments: (1) Source to P1, (2) P1 to destination_01, and (3) P2 to destination_02.

Source

netwo

rk 1

Net_1

R C

Source

P1

Destination_01

Destination_02

R C

netwo

rk 2

R C

netwo

rk 3

Destination_01

Destination_02

P1

Fig. 1 - Example of a net going to multiple destinations and its model in proposed method


Page 02 of 5

     Current methods for parasitic measurement cannot isolate capacitance for a net segment. They provide parasitic capacitance for the whole net or individual capacitances for each participating parasitic. User intelligence is needed to divide the total capacitance among the different net segments, which can cause inaccuracy. Also, after finding R and C for net segments, parasitic RC models are applied to the schematic. Current methods use Elmore model or pi network model having single or multiple stages. There are issues due to trade-off of model complexity and accuracy with these techniques, so a simple and accurate model for back annotating net segment's R & C...