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A Method for Hotspot Elimination in VLSI Circuits via Temperature-Aware Placement Optimization

IP.com Disclosure Number: IPCOM000245419D
Publication Date: 2016-Mar-08
Document File: 6 page(s) / 286K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to pre-characterize a standard cell library for thermal/power effect in order to eliminate hotspots in Very Large Scale Integration (VLSI) circuits.

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A Method for Hotspot Elimination in VLSI Circuits via Temperature -Aware Placement Optimization

In the physical design process of microprocessors/systems on chip (SOC), with a rise in the switching speed in the Very Large Scale Integration (VLSI) circuits, the probability of a large number of cells switching in a short period of time increases. A large number of simultaneous switching occurring in a short period can cause a considerable amount of noise in the power supply network of a circuit and can cause local thermal hotspots. Power supply noise results in a decrease in the voltage for cell Power Ground nodes.

During the placement process, there are many available and emerging techniques to address thermal and IR drop issues by altering placement options of different components. The Large Block Synthesis (LBS) paradigm deals with multi-millions of cells; a deeper understanding of the likelihood of issues is needed as early as possible in the design cycle in order to avoid many iterative fixes. This subsequently has a great impact on design convergence and turnaround time.

A method for the pre-characterization of a standard cell library for thermal/power effect is needed.

The novel contribution is a method to pre-characterize a standard cell library for thermal/power effect. The method scores each library cell based on thermal/power characteristics. This is a one-time process before the Physical Design (PD) flow. Multiple scores are possible per library cell for the range of expected Cloadvalues. The library cell score is used for placement optimization in the PD flow. During global placement optimization, the method uses pre-characterized thermal/power scores in the global placement objective function. During local placement optimization, the method applies local placement optimization techniques to rearrange cells for better thermal/IR drop profile and to flatten the thermal/IR drop profile. In addition, the method uses pre-characterization and "in-flight" scores to estimate/optimize the thermal/IR drop profile.

The Temperature Difficulty Scoring (TDS) scheme for library follows:

1. Temperature Difficulty Score (TDS): a parameter or a weight given to each standard cell of the standard cell library based on how much each standard cell is likely to contribute to the components of power dissipation


2. TDS of a standard cell = F (Cload , Switching Factor (SF), Gate Width, Vt factor)

3. Currently, internal cap is not estimated and assumes a multiplication factor of 1.1 (10% of output load)

The equation to calculate the relative score (TDS) for the standard cells is:


1. TDS = (PDk + PLk)where PDk is the dynamic power and PLk is the leakage power of the standardcell

1


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2. TDS = {0.5 * (Cload * V2* F * S)} + {(...