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Integrated Anti-Fuse with Reduced Programming Voltage

IP.com Disclosure Number: IPCOM000245439D
Publication Date: 2016-Mar-10
Document File: 4 page(s) / 83K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method and structure for forming anti-fuse structure along with a MOSFET transistor to form on-chip antifuse. An electrode of the antifuse is sharpened to to reduce the anti-fuse programming voltage.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 82% of the total text.

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Integrated Anti -

Anti-fuses have a variety of applications. The conventional anti-fuse uses the same gate dielectric as the Field Effect Transistors (FETs). Consequently, the breakdown voltage (i.e., programming voltage) of the anti-fuse is high (e.g., the breakdown voltage is ~4V for the state-of-the-art gate dielectric). It is desired to have on-chip anti-fuse with reduced programming voltage.

This solution provides a method and structure for forming anti-fuse structure along with a MOSFET transistor to form on-chip antifuse. An electrode of the antifuse is sharpened to to reduce the anti-fuse programming voltage.

Figure 1: Anti-fuse has a pointed top to reduce programming (breakdown) voltage. The conductive cathode has a pointy tip. A dielectric is coated on the cathode. A conductive anode is deposited on top of the dielectric .

Figure 2: Anti-fuse and FinFET are formed on the same chip (sharing common processes)

-Fuse with Reduced Programming Voltage

Fuse with Reduced Programming Voltage

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The process flow follows:


1. Start with a semiconductor substrate (e.g., bulk Silicon (Si) substrate)


2. Form transistor in one area and save another area for antifuse .

Figure 3: Use a mask to cover the transistor region. Perform an etch to form anti-fuse trench.


3. Form anti-fuse cathode by depositing a pointy conductor.

Figure 4: a pointy cathode is formed in the trench. The pointy top can can be formed by electrochemical etch to sharpen a metal.

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