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Integrated Circuit with Vertical CMOS and Tunnel FETs

IP.com Disclosure Number: IPCOM000245529D
Publication Date: 2016-Mar-15
Document File: 5 page(s) / 56K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed are a method and structure for integrating Tunnel Field Effect Transistors (TFETs) and Metal-Oxide Field Effect Transistors (MOSFETs) on the same chip in a cost-effective manner.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 85% of the total text.

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Integrated Circuit with Vertical CMOS and Tunnel FETs

Tunnel Field Effect Transistors (TFETs) have the advantage of sub-60mV/dec subthreshold swing, but also have the disadvantage of low drive current. To render TFETs useful at circuit level requires the integration of Metal-Oxide Field Effect Transistors (MOSFETs) integrated along with TFETs, so that MOSFETs can be used in the circuit where high drive current is needed. The integration of TFETs and MOSFETs is not trivial because MOSFETs are structurally symmetric (i.e., source/drain are the same), whereas TEFTs are structurally asymmetric (i.e., source and drain must have different dopant polarities).

Therefore, there is a need for integrating TFETs with MOSFETs in a cost-effective way.

The novel solution is a method and structure for integrating TFETs and MOSFETs on the same chip.

Figure 1 illustrates the final structure with this solution applied. Shown an N-type MOSFET and an n-type TFET.

Figure 1: Final Structure

Following are the steps for the process flow in a preferred embodiment.

Start with a substrate, form fins for MOSFET and TFET with bottom bottom source/drain

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Fig. 2 after forming fins for NMOSFET and nTFET

Then gate stack with high-k gate dielectric and metal gate are formed around fins.

Spacers can be formed before forming the gate stack.

Figure 3: after forming gate stack with high-k gate dielectric and

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Then recess metal gate. The recess can be done by reactive ion e...