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Electrical Measurements based kitting in 3D Integrated Circuits

IP.com Disclosure Number: IPCOM000245558D
Publication Date: 2016-Mar-16
Document File: 4 page(s) / 147K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for electrical measurements based kitting in 3D integrated circuits (IC). This method provides an optimized form of timing closure with reduced pessimism.

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Title

Electrical Measurements based kitting in 3D Integrated Circuits

Abstract

Disclosed is a method for electrical measurements based kitting in 3D integrated circuits (IC). This method provides an optimized form of timing closure with reduced pessimism.

Problem

Three-dimensional (3D) chip stacking allows the combining of dies from multiple technologies, which is advantageous. Die produced by different processes have different resistance-capacitance (R/C) profiles; therefore, timing needs to cover full R/C range (BC and WC) for multiple technologies. Timing must currently account for full distribution of both R/C distributions across multiple processes. Timing closure can be optimized by separating die into resistance/capacitance-matched groups. Timing analysis can be executed in anticipation of matched groups.

Figure 1: R/C matched dies

Figure 2: Timing

Solution/Novel Contribution

The novel contribution is a method for electrical measurements based kitting in 3D integrated circuits (IC). The solution comprises methods and components to:

• Optimize the design of 3D Products by defining the allowed R/C combinations between two or more dies as well as defining the timing R/C ranges for each die


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going into each allowed 3D combination. Optimization also includes timing each die using the allowed R/C value.

• Manufacture the 3D product. The method records R/C for each wafer and/or die and then separates parts into groups meeting allowed R/C values (by part number or other means). Using the allowed R/C kits, the method combines fabricating 3D assemblies.

• Optimize the timing analysis of integrated circuits. The method first determines distributions of resistance and capacitances for a select process, and then allocates the distributions to an R/C bin. Products are timed separately based on anticipated R/C distributions and are separate...