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Method for Fabricating a Vertical FET with Air-Gap Top Spacer

IP.com Disclosure Number: IPCOM000245671D
Publication Date: 2016-Mar-28
Document File: 5 page(s) / 202K

Publishing Venue

The IP.com Prior Art Database

Abstract

The method provides a fabrication process for forming air-gape inside the top spacer.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 80% of the total text.

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Method for Fabricating a Vertical FET with Air -

Vertical transistors are getting lot of interests these days due to vertical transistors' potential for further area scaling. Therefore, it is one of key candidates for 5nm and beyond CMOS technology.

Existing fabrication processes need a top spacer (SiN or low k spacer) to separate gate and top SD. However, parasitic capacitance between top SD to gate may hamper performance of a device.

The disclosed method provides a fabrication process for forming air -gape inside the top spacer.

Following figures (FIG. 1 to FIG. 10) illustrates the fabrication steps in accordance with the method disclosed herein.

FIG. 1 illustrates a step of forming a vertical FIN by FIN patterning and a step of bottom spacer formation.

FIG. 1

Moving on, FIG. 2 illustrates a step of lateral FIN trimming and a step of forming High K and WFM

FIG. 2

-Gap Top Spacer

Gap Top Spacer

1


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FIG. 3 illustrates the step of etching WFM and high K and the step of W gate deposition.

FIG. 3

FIG. 4 illustrates the steps of W gate CMP, W recess and lateral etching of the WFM .

FIG. 4

FIG. 5 illustrates the steps of thin SiN or low K film deposition and forming air -gap by depositing oxide.

2


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FIG. 5

FIG. 6 illustrates the steps of removal of SiN HM.

FIG. 6

FIG. 7 illustrates the step of forming a SiN inner spacer.

FIG. 7

3


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FIG. 8 illustrates the steps of recessing of the channel for forming an overlap region and growing doped...