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REMOVING POWER VIA STUB EFFECTS ON HIGH SPEED DIFFERENTIAL (HSD) SIGNALS WHERE HSD SIGNALS ARE SURROUNDED BY GROUND AND POWER VIAS IN PRINTED CIRCUIT BOARDS

IP.com Disclosure Number: IPCOM000245690D
Publication Date: 2016-Mar-30
Document File: 3 page(s) / 241K

Publishing Venue

The IP.com Prior Art Database

Related People

Il-Young Park: AUTHOR [+2]

Abstract

According to a first solution, power via stub effects are addressed by adding traces between power vias. Trace/traces can be added to inner or bottom layer of print circuit boards while preserving decoupling capacitors for power delivery. In accordance with a second solution, power via stub effects are solved by adding a 100 ohm resistor termination between power vias on the bottom of the board when power plane layer is in upper half of the print circuit board layer and chip sits on the top layer, and vice versa. These solutions lower cost of package by providing an option for chip ball grid array (BGA) ball map where high speed differential (HSD) signals are surrounded by ground and power pins without power via stub effect, and avoids the need to consider bigger packages where HSD signals are surrounded by ground pins only.

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  REMOVING POWER VIA STUB EFFECTS ON HIGH SPEED DIFFERENTIAL (HSD) SIGNALS WHERE HSD SIGNALS ARE SURROUNDED BY GROUND AND

POWER VIAS IN PRINTED CIRCUIT BOARDS

  AUTHORS: Il-Young Park Jayanthi Natarajan

CISCO SYSTEMS, INC. Peerouz Amleshi

Pu Xie

MOLEX, INC.

ABSTRACT

    According to a first solution, power via stub effects are addressed by adding traces between power vias. Trace/traces can be added to inner or bottom layer of print circuit boards while preserving decoupling capacitors for power delivery. In accordance with a second solution, power via stub effects are solved by adding a 100 ohm resistor termination between power vias on the bottom of the board when power plane layer is in upper half of the print circuit board layer and chip sits on the top layer, and vice versa. These solutions lower cost of package by providing an option for chip ball grid array (BGA) ball map where high speed differential (HSD) signals are surrounded by ground and power pins without power via stub effect, and avoids the need to consider bigger packages where HSD signals are surrounded by ground pins only.

DETAILED DESCRIPTION

    In a chip ball grid array (BGA) ball map, where high speed differential (HSD) signals are surrounded by any number of power pins/vias, power via stub effects becomes apparent at 12 GHz or higher, and this significantly affects HSD signal integrity.

    HSD signals surrounded by any number of power pins/vias will have significant performance drop in insertion loss, return loss and crosstalk amplification because power vias behave as resonator. HSD signal performance degradation can be so significant such

Copyright 2016 Cisco Systems, Inc.
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that some HSD signals are likely to have bit drops, traffic failures, and inferior bit error rates. This performance degradation will get worse as HSD signals run faster.

    Accordingly, a first solution is presented here in which the power via stub impact is reduced by adding traces between the power vias. The number and location of the traces...