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Self-Aligned Gate Isolation Process for FINFET CMOS beyond 10nm

IP.com Disclosure Number: IPCOM000245702D
Publication Date: 2016-Mar-31
Document File: 6 page(s) / 160K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a self-aligned gate isolation process for a fin Field Effect Transistor (FINFET) Complementary Metal Oxide Semiconductor (CMOS) process beyond 10nm. The approach is to create a dummy fin at the place where gate isolation is needed and replace the dummy fin material with dielectrics. The isolation has a self-aligned gate isolation process and gate isolation as narrow as the FIN width (well below 20nm).

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Title

Self-Aligned Gate Isolation Process for FINFET CMOS beyond 10nm

Abstract

Disclosed is a self-aligned gate isolation process for a fin Field Effect Transistor (FINFET) Complementary Metal Oxide Semiconductor (CMOS) process beyond 10nm. The approach is to create a dummy fin at the place where gate isolation is needed and replace the dummy fin material with dielectrics. The isolation has a self-aligned gate isolation process and gate isolation as narrow as the FIN width (well below 20nm).

Problem

In the Complementary Metal Oxide Semiconductor (CMOS) process, poly gate isolation is done by using a so-called "cut" process to break the continuity of a poly gate line and then fill the gap with dielectrics (since 32nm CMOS technology). This process can help achieve a small space between the poly gate and hence develop a denser design. However, due to the limitations of the optical lithography system, making poly gate isolation smaller than 20nm as well as keeping the isolate sufficiently away from the active gate area is extremely challenging. In 7nm CMOS technology, a poly gate cut of less than 20nm wide is needed.

Poly gate cut is needed for gate isolation. A large space (S) is needed to be able to fill the gate material, set the work function, and hence Vt for Metal Oxide on Semiconductor Field Effect Transistor (MOSFET). Width (W) must be as small as possible because the space between two fins is normally fixed. W is affected by the litho-printing capability, S is affected by overlay between fin and the poly gate cut. In 7nm technology, W needs to be less than 20nm in order to have proper S. However, the current tool set cannot support that.

Figure 1: Patterning/overlay limitation


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Figure 2: Pr...