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PRE-LAYOUT SCHEMATIC LEVEL POWER DISTRIBUTION NETWORK VISUALIZATION AND ANALYSIS

IP.com Disclosure Number: IPCOM000245724D
Publication Date: 2016-Apr-01
Document File: 4 page(s) / 131K

Publishing Venue

The IP.com Prior Art Database

Related People

Amendra Koul: AUTHOR [+5]

Abstract

A method is provided to run a power distribution analysis that processes the schematic using a step called a power tree to visualize power distribution network, run pre-layout simulation and reuse data for easier hardware design.

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PRE-LAYOUT SCHEMATIC LEVEL POWER DISTRIBUTION NETWORK VISUALIZATION AND ANALYSIS

 AUTHORS: Amendra Koul Brian Baek Jason Visneski

Mike Sapozhnikov Jiali Lai

CISCO SYSTEMS, INC.

ABSTRACT

    A method is provided to run a power distribution analysis that processes the schematic using a step called a power tree to visualize power distribution network, run pre-layout simulation and reuse data for easier hardware design.

DETAILED DESCRIPTION

     Power integrity (PI) analysis for boards that have multiple power rails with many source/sink components is complex and very time consuming. Typically, it is an iterative process to optimize the Power Distribution Network (PDN). A well designed PDN is essential for the reliable operation of the chips and circuits in a system.

    Current PDN analysis techniques have many limitations. One of the biggest problems is that it is necessary to wait for the layout to be finished before PDN analysis can begin. Every power net must also be identified, and with many power nets spread across large schematics with many pages, this is a time consuming and error prone activity. Achieving an understanding of the full PDN with all its paths and levels requires creating even more documentation. That documentation is usually a hand-drawn visualization of the PDN. Excessive voltage drop across filter nets is a common problem, but is typically identified at the end of design cycle when it is more complicated to fix. Tracking how schematic changes affect the PDN as the design moves forward is also very challenging. The changes can be subtle and hard to identify, and the different tools in the design flow can be out of sync. Finally, the ability to reuse data as schematic changes occur and to reuse old data for new designs is limited.

Copyright 2016 Cisco Systems, Inc.
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    Currently, solutions only exist for some of these problems and those are solved late in the design cycle after a layout file is present. This increases the design time and resources required, and can ultimately hinder quality, cost, and time to market.

    Figure 1 shows a typical Power Integrity (PI) method. The analysis occurs after receiving a layout file. This layout file is then imported by a PI simulation tool, and then all the data for simulation can be entered. Compiling, entering, and error checking all the data is an iterative p...