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Method for complex mixed-signal IP simulation and verification

IP.com Disclosure Number: IPCOM000245858D
Publication Date: 2016-Apr-13
Document File: 6 page(s) / 403K

Publishing Venue

The IP.com Prior Art Database

Abstract

Functional verification of complex mixed-signal IPs (i.e. analog circuits with logic functions embedded and/or that rely on logic control to work) is a task of increasing importance. The natural choice to perform this is to employ AMS (analog mixed signal) simulators by analog designers and verification engineers. However, they have different interests, approaches and methods to perform their work. One can say that there are two different flows: designers are concerned to satisfy performance requirements and normally use "schematic-based/gui" tools; verification engineers are concerned to validate system integration/operation using "text-based/command-line" tools. A work method and an "apparatus" is presented. It helps both designers and verification engineers to promptly assembly simulation testbench and stimuli cases at their working environments even at early phases of IP design. The proposed method makes the flows closer facilitating communication and information exchange.

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Method for complex mixed-signal IP simulation and verification

Abstract

Functional verification of complex mixed-signal IPs (i.e. analog circuits with logic functions embedded and/or that rely on logic control to work) is a task of increasing importance. The natural choice to perform this is to employ AMS (analog mixed signal) simulators by analog designers and verification engineers. However, they have different interests, approaches and methods to perform their work. One can say that there are two different flows: designers are concerned to satisfy performance requirements and normally use "schematic-based/gui" tools; verification engineers are concerned to validate system integration/operation using "text-based/command-line" tools.

A work method and an "apparatus" is presented. It helps both designers and verification engineers to promptly assembly simulation testbench and stimuli cases at their working environments even at early phases of IP design. The proposed method makes the flows closer facilitating communication and information exchange.

Introduction

As System-on-Chip (SoC) ICs increase their complexity, so do the analog IPs required to be integrated on them. A hypothetical illustrative example could be a pure analog IP as a LDO (low dropout voltage regulator) circuit that originally can be designed using schematic entry, electrical simulation plus (optionally) layout parasitic extraction to be accomplished. However, if this very same circuit is part of a more complex (now a mixed-signal) IP like a DVS (dynamic voltage scaling) system, more design and verification requirements are added and more effort is needed. Traditional "schematic-based/gui" is inefficient to create stimuli for a variety of operating scenarios, particularly cases that involve logic feedback to control circuit behavior. On the other side, adopting an AMS simulator has its problems; coding a complete Verilog/VerilogAMS (or equivalent) stimulus can be difficult or even intimidating for many of analog designers and verification engineers may not help, since they use a completely different work environment and experience exchange even to reproduce a potential issue becomes a hard task.

The approach employed to eliminate these problems, is to create and partition (mainly) testbenches in "schematic-based/gui" flow (optionally testbench netlists used on "text-based/command-line" flow) using elements from a verification component library - DA_VIP_AMS. This library takes advantage of some


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common concepts and practices used on digital verification world and adapt them such way that can be used by both "schematic-based/gui" or "text-based/command-line" flows. This approach makes testbench creation standardized (easy to automate), simplify stimuli creation and make the flows closer to each other so that information exchange now is possible.

Structure and Implementation

The DA_VIP_AMS is the "apparatus", a versioned library containing:

1) Stimuli en...