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Vertical FET Multiple Vt Realization by Gate Pitch Patterning

IP.com Disclosure Number: IPCOM000245925D
Publication Date: 2016-Apr-18
Document File: 5 page(s) / 219K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to implement multiple wafer fabricated (WF) metals for Vt adjustment for vertical Field Effect Transistors (FETs) by gate pitch patterning, with no extra mask added.

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Vertical FET Multiple Vt Realization by Gate Pitch Patterning

The use of vertical Field Effect Transistors (FETs) is promising for future Metal-Oxide Semiconductor (MOS) FET scaling beyond 7nm. One challenge, however, is achieving the multi-Vt for design application.

The novel contribution is a method to implement multiple wafer fabricated (WF) metals for Vt adjustment for vertical FETs by gate pitch patterning, with no extra mask added.

The following figures represent the steps to implement this method in a preferred embodiment.

Figure 1: Starting substrate

Figure 2: After FIN patterning, FIN cut and shallow trench isolation (STI) formation

Figure 3: Gas Cluster Ion Beam (GCIB) Silicon Nitride (SiN) for bottom spacer

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Figure 4: Dummy gate dep and Chemical Mechanical Planarization (CMP)

Figure 5: a-Si recess

Figure 6: SiN fill and CMP

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Figure 7: PC patterning for multiple gate pitch

Figure 8: Selective material removal (e.g., selective Silicon Germanium (SiGe) removal to Si)

Figure 9: Oxide etch

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Figure 10: SiN spacer formation

Figure 11: Heavily doped S/D epi formation

Figure 12: Oxide fill and Point of Connection (POC)

Figure 13: SiN open

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Figure 14: Dummy a-Si and oxide removal

Figure 15: HK & composite metal gate Titanium Nitride/Titanium Carbide(TiN/TiC) depo for FET 1 and FET 2 (No patterning needed)

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