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Algorithm for ADC Static Linearity Check

IP.com Disclosure Number: IPCOM000245981D
Publication Date: 2016-Apr-21

Publishing Venue

The IP.com Prior Art Database

Abstract

The demand for high precision accuracy has led to much advanced innovation over the past few years. High performance analog-to-digital converters (ADCs) that feature outstanding specifications and performance often ignored parameters like linearity, which also should be included in the verification methodology. In an ADC/ Digital-to-analog Converters (DAC), we are concerned with two measures of the linearity of its transfer function: integral nonlinearity or relative accuracy (INL), and differential nonlinearity (DNL). INL is the maximum deviation at any point in the transfer function of the output voltage level from its ideal value, which is a straight line drawn through the actual zero and full-scale of the DAC. DNL is the maximum deviation of an actual analog output step, between adjacent input codes, from the ideal step value of +1 LSB, calibrated based on the gain of the particular DAC. If the DNL is more negative than –1 LSB, the DACs transfer function is non-monotonic. Since running these tests requires a large time from a simulation perspective, ways to shorten this process are needed. Further, during tester validation, there is a continuous drive to reduce the testing time on tester. This too opens the gate for an innovative algorithm to reduce tester time.

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Page 01 of 10

Algorithm for ADC Static Linearity Check

Abstract

The demand for high precision accuracy has led to much advanced innovation over the past few years. High performance analog-to-digital converters (ADCs) that feature outstanding specifications and performance often ignored parameters like linearity, which also should be included in the verification methodology. In an ADC/ Digital-to-analog Converters (DAC), we are concerned with two measures of the linearity of its transfer function: integral nonlinearity or relative accuracy (INL), and differential nonlinearity (DNL). INL is the maximum deviation at any point in the transfer function of the output voltage level from its ideal value, which is a straight line drawn through the actual zero and full-scale of the DAC. DNL is the maximum deviation of an actual analog output step, between adjacent input codes, from the ideal step value of +1 LSB, calibrated based on the gain of the particular DAC. If the DNL is more negative than -1 LSB, the DACs transfer function is non-monotonic. Since running these tests requires a large time from a simulation perspective, ways to shorten this process are needed. Further, during tester validation, there is a continuous drive to reduce the testing time on tester. This too opens the gate for an innovative algorithm to reduce tester time.

Introduction

     The test for static linearity (INL, DNL) of high-performance SAR ADCs is challenging as it is expensive in terms of test time and memory requirements. Test time increases drastically with resolution of ADCs and required accuracy of DNL & INL. Traditional test methods for static linearity of SAR ADCs are (i) servo-loop method - seldom used nowadays due to sensitivity to noise and test time And (ii) histogram method, which requires enormous test time and memory. In this paper we propose a method that targets significant reduction in tester (simulator) resources (time & memory) while increasing accuracy of measured non-linearity figures of SAR ADCs.

Current Approach

 Servo Loop Method



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Figure 1: Servo-Loop Setup

 Integrator input is a constant voltage (±V)
 Integrator output is a ramp and is converted by ADC (output A)
 ADC output (A) is compared against next code (B) using comparator

When A>B, input ramp is decreased When A>B, input ramp is increased

 Hence, transition point of code is found in multiple iterations

Limitations

 Increasingly higher sampling rate and higher input bandwidth leads to higher input referred noise due to resistor noise and KT/C noise

 This method cannot be used in applications where Spurious-Free Dynamic Range (SFDR) is performance limiting specification

 Test time drastically increases with accuracy of measurement


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 Histogram Test with Linear Ramp Input

Figure 2: Histogram Test with Linear Ramp Input

 Assuming 16 hits per code for a 12bit ADC, with 1MSPS, the total conversions is 65536  This is equivalent to 65.536ms of inp...